/* SPDX-License-Identifier: GPL-2.0 */ /* * MUSB OTG driver register defines * * Copyright 2005 Mentor Graphics Corporation * Copyright (C) 2005-2006 by Texas Instruments * Copyright (C) 2006-2007 Nokia Corporation */ #ifndef __MUSB_REGS_H__ #define __MUSB_REGS_H__ #define MUSB_EP0_FIFOSIZE … /* * MUSB Register bits */ /* POWER */ #define MUSB_POWER_ISOUPDATE … #define MUSB_POWER_SOFTCONN … #define MUSB_POWER_HSENAB … #define MUSB_POWER_HSMODE … #define MUSB_POWER_RESET … #define MUSB_POWER_RESUME … #define MUSB_POWER_SUSPENDM … #define MUSB_POWER_ENSUSPEND … /* INTRUSB */ #define MUSB_INTR_SUSPEND … #define MUSB_INTR_RESUME … #define MUSB_INTR_RESET … #define MUSB_INTR_BABBLE … #define MUSB_INTR_SOF … #define MUSB_INTR_CONNECT … #define MUSB_INTR_DISCONNECT … #define MUSB_INTR_SESSREQ … #define MUSB_INTR_VBUSERROR … /* DEVCTL */ #define MUSB_DEVCTL_BDEVICE … #define MUSB_DEVCTL_FSDEV … #define MUSB_DEVCTL_LSDEV … #define MUSB_DEVCTL_VBUS … #define MUSB_DEVCTL_VBUS_SHIFT … #define MUSB_DEVCTL_HM … #define MUSB_DEVCTL_HR … #define MUSB_DEVCTL_SESSION … /* BABBLE_CTL */ #define MUSB_BABBLE_FORCE_TXIDLE … #define MUSB_BABBLE_SW_SESSION_CTRL … #define MUSB_BABBLE_STUCK_J … #define MUSB_BABBLE_RCV_DISABLE … /* MUSB ULPI VBUSCONTROL */ #define MUSB_ULPI_USE_EXTVBUS … #define MUSB_ULPI_USE_EXTVBUSIND … /* ULPI_REG_CONTROL */ #define MUSB_ULPI_REG_REQ … #define MUSB_ULPI_REG_CMPLT … #define MUSB_ULPI_RDN_WR … /* TESTMODE */ #define MUSB_TEST_FORCE_HOST … #define MUSB_TEST_FIFO_ACCESS … #define MUSB_TEST_FORCE_FS … #define MUSB_TEST_FORCE_HS … #define MUSB_TEST_PACKET … #define MUSB_TEST_K … #define MUSB_TEST_J … #define MUSB_TEST_SE0_NAK … /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ #define MUSB_FIFOSZ_DPB … /* Allocation size (8, 16, 32, ... 4096) */ #define MUSB_FIFOSZ_SIZE … /* CSR0 */ #define MUSB_CSR0_FLUSHFIFO … #define MUSB_CSR0_TXPKTRDY … #define MUSB_CSR0_RXPKTRDY … /* CSR0 in Peripheral mode */ #define MUSB_CSR0_P_SVDSETUPEND … #define MUSB_CSR0_P_SVDRXPKTRDY … #define MUSB_CSR0_P_SENDSTALL … #define MUSB_CSR0_P_SETUPEND … #define MUSB_CSR0_P_DATAEND … #define MUSB_CSR0_P_SENTSTALL … /* CSR0 in Host mode */ #define MUSB_CSR0_H_DIS_PING … #define MUSB_CSR0_H_WR_DATATOGGLE … #define MUSB_CSR0_H_DATATOGGLE … #define MUSB_CSR0_H_NAKTIMEOUT … #define MUSB_CSR0_H_STATUSPKT … #define MUSB_CSR0_H_REQPKT … #define MUSB_CSR0_H_ERROR … #define MUSB_CSR0_H_SETUPPKT … #define MUSB_CSR0_H_RXSTALL … /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ #define MUSB_CSR0_P_WZC_BITS … #define MUSB_CSR0_H_WZC_BITS … /* TxType/RxType */ #define MUSB_TYPE_SPEED … #define MUSB_TYPE_SPEED_SHIFT … #define MUSB_TYPE_PROTO … #define MUSB_TYPE_PROTO_SHIFT … #define MUSB_TYPE_REMOTE_END … /* CONFIGDATA */ #define MUSB_CONFIGDATA_MPRXE … #define MUSB_CONFIGDATA_MPTXE … #define MUSB_CONFIGDATA_BIGENDIAN … #define MUSB_CONFIGDATA_HBRXE … #define MUSB_CONFIGDATA_HBTXE … #define MUSB_CONFIGDATA_DYNFIFO … #define MUSB_CONFIGDATA_SOFTCONE … #define MUSB_CONFIGDATA_UTMIDW … /* TXCSR in Peripheral and Host mode */ #define MUSB_TXCSR_AUTOSET … #define MUSB_TXCSR_DMAENAB … #define MUSB_TXCSR_FRCDATATOG … #define MUSB_TXCSR_DMAMODE … #define MUSB_TXCSR_CLRDATATOG … #define MUSB_TXCSR_FLUSHFIFO … #define MUSB_TXCSR_FIFONOTEMPTY … #define MUSB_TXCSR_TXPKTRDY … /* TXCSR in Peripheral mode */ #define MUSB_TXCSR_P_ISO … #define MUSB_TXCSR_P_INCOMPTX … #define MUSB_TXCSR_P_SENTSTALL … #define MUSB_TXCSR_P_SENDSTALL … #define MUSB_TXCSR_P_UNDERRUN … /* TXCSR in Host mode */ #define MUSB_TXCSR_H_WR_DATATOGGLE … #define MUSB_TXCSR_H_DATATOGGLE … #define MUSB_TXCSR_H_NAKTIMEOUT … #define MUSB_TXCSR_H_RXSTALL … #define MUSB_TXCSR_H_ERROR … /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ #define MUSB_TXCSR_P_WZC_BITS … #define MUSB_TXCSR_H_WZC_BITS … /* RXCSR in Peripheral and Host mode */ #define MUSB_RXCSR_AUTOCLEAR … #define MUSB_RXCSR_DMAENAB … #define MUSB_RXCSR_DISNYET … #define MUSB_RXCSR_PID_ERR … #define MUSB_RXCSR_DMAMODE … #define MUSB_RXCSR_INCOMPRX … #define MUSB_RXCSR_CLRDATATOG … #define MUSB_RXCSR_FLUSHFIFO … #define MUSB_RXCSR_DATAERROR … #define MUSB_RXCSR_FIFOFULL … #define MUSB_RXCSR_RXPKTRDY … /* RXCSR in Peripheral mode */ #define MUSB_RXCSR_P_ISO … #define MUSB_RXCSR_P_SENTSTALL … #define MUSB_RXCSR_P_SENDSTALL … #define MUSB_RXCSR_P_OVERRUN … /* RXCSR in Host mode */ #define MUSB_RXCSR_H_AUTOREQ … #define MUSB_RXCSR_H_WR_DATATOGGLE … #define MUSB_RXCSR_H_DATATOGGLE … #define MUSB_RXCSR_H_RXSTALL … #define MUSB_RXCSR_H_REQPKT … #define MUSB_RXCSR_H_ERROR … /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ #define MUSB_RXCSR_P_WZC_BITS … #define MUSB_RXCSR_H_WZC_BITS … /* HUBADDR */ #define MUSB_HUBADDR_MULTI_TT … /* * Common USB registers */ #define MUSB_FADDR … #define MUSB_POWER … #define MUSB_INTRTX … #define MUSB_INTRRX … #define MUSB_INTRTXE … #define MUSB_INTRRXE … #define MUSB_INTRUSB … #define MUSB_INTRUSBE … #define MUSB_FRAME … #define MUSB_INDEX … #define MUSB_TESTMODE … /* * Additional Control Registers */ #define MUSB_DEVCTL … #define MUSB_BABBLE_CTL … /* These are always controlled through the INDEX register */ #define MUSB_TXFIFOSZ … #define MUSB_RXFIFOSZ … #define MUSB_TXFIFOADD … #define MUSB_RXFIFOADD … /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */ #define MUSB_HWVERS … #define MUSB_ULPI_BUSCONTROL … #define MUSB_ULPI_INT_MASK … #define MUSB_ULPI_INT_SRC … #define MUSB_ULPI_REG_DATA … #define MUSB_ULPI_REG_ADDR … #define MUSB_ULPI_REG_CONTROL … #define MUSB_ULPI_RAW_DATA … #define MUSB_EPINFO … #define MUSB_RAMINFO … #define MUSB_LINKINFO … #define MUSB_VPLEN … #define MUSB_HS_EOF1 … #define MUSB_FS_EOF1 … #define MUSB_LS_EOF1 … /* Offsets to endpoint registers */ #define MUSB_TXMAXP … #define MUSB_TXCSR … #define MUSB_CSR0 … #define MUSB_RXMAXP … #define MUSB_RXCSR … #define MUSB_RXCOUNT … #define MUSB_COUNT0 … #define MUSB_TXTYPE … #define MUSB_TYPE0 … #define MUSB_TXINTERVAL … #define MUSB_NAKLIMIT0 … #define MUSB_RXTYPE … #define MUSB_RXINTERVAL … #define MUSB_FIFOSIZE … #define MUSB_CONFIGDATA … #include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */ #define MUSB_TXCSR_MODE … /* "bus control"/target registers, for host side multipoint (external hubs) */ #define MUSB_TXFUNCADDR … #define MUSB_TXHUBADDR … #define MUSB_TXHUBPORT … #define MUSB_RXFUNCADDR … #define MUSB_RXHUBADDR … #define MUSB_RXHUBPORT … static inline u8 musb_read_configdata(void __iomem *mbase) { … } static inline void musb_write_rxfunaddr(struct musb *musb, u8 epnum, u8 qh_addr_reg) { … } static inline void musb_write_rxhubaddr(struct musb *musb, u8 epnum, u8 qh_h_addr_reg) { … } static inline void musb_write_rxhubport(struct musb *musb, u8 epnum, u8 qh_h_port_reg) { … } static inline void musb_write_txfunaddr(struct musb *musb, u8 epnum, u8 qh_addr_reg) { … } static inline void musb_write_txhubaddr(struct musb *musb, u8 epnum, u8 qh_addr_reg) { … } static inline void musb_write_txhubport(struct musb *musb, u8 epnum, u8 qh_h_port_reg) { … } static inline u8 musb_read_rxfunaddr(struct musb *musb, u8 epnum) { … } static inline u8 musb_read_rxhubaddr(struct musb *musb, u8 epnum) { … } static inline u8 musb_read_rxhubport(struct musb *musb, u8 epnum) { … } static inline u8 musb_read_txfunaddr(struct musb *musb, u8 epnum) { … } static inline u8 musb_read_txhubaddr(struct musb *musb, u8 epnum) { … } static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum) { … } #endif /* __MUSB_REGS_H__ */
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