/* SPDX-License-Identifier: GPL-2.0 */ /* * ci.h - common structures, functions, and macros of the ChipIdea driver * * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. * * Author: David Lopo */ #ifndef __DRIVERS_USB_CHIPIDEA_CI_H #define __DRIVERS_USB_CHIPIDEA_CI_H #include <linux/list.h> #include <linux/irqreturn.h> #include <linux/usb.h> #include <linux/usb/gadget.h> #include <linux/usb/otg-fsm.h> #include <linux/usb/otg.h> #include <linux/usb/role.h> #include <linux/ulpi/interface.h> /****************************************************************************** * DEFINE *****************************************************************************/ #define TD_PAGE_COUNT … #define CI_HDRC_PAGE_SIZE … #define ENDPT_MAX … #define CI_MAX_BUF_SIZE … /****************************************************************************** * REGISTERS *****************************************************************************/ /* Identification Registers */ #define ID_ID … #define ID_HWGENERAL … #define ID_HWHOST … #define ID_HWDEVICE … #define ID_HWTXBUF … #define ID_HWRXBUF … #define ID_SBUSCFG … /* register indices */ enum ci_hw_regs { … }; /****************************************************************************** * STRUCTURES *****************************************************************************/ /** * struct ci_hw_ep - endpoint representation * @ep: endpoint structure for gadget drivers * @dir: endpoint direction (TX/RX) * @num: endpoint number * @type: endpoint type * @name: string description of the endpoint * @qh: queue head for this endpoint * @wedge: is the endpoint wedged * @ci: pointer to the controller * @lock: pointer to controller's spinlock * @td_pool: pointer to controller's TD pool */ struct ci_hw_ep { … }; enum ci_role { … }; enum ci_revision { … }; /** * struct ci_role_driver - host/gadget role driver * @start: start this role * @stop: stop this role * @suspend: system suspend handler for this role * @resume: system resume handler for this role * @irq: irq handler for this role * @name: role name string (host/gadget) */ struct ci_role_driver { … }; /** * struct hw_bank - hardware register mapping representation * @lpm: set if the device is LPM capable * @phys: physical address of the controller's registers * @abs: absolute address of the beginning of register window * @cap: capability registers * @op: operational registers * @size: size of the register window * @regmap: register lookup table */ struct hw_bank { … }; /** * struct ci_hdrc - chipidea device representation * @dev: pointer to parent device * @lock: access synchronization * @hw_bank: hardware register mapping * @irq: IRQ number * @roles: array of supported roles for this controller * @role: current role * @is_otg: if the device is otg-capable * @fsm: otg finite state machine * @otg_fsm_hrtimer: hrtimer for otg fsm timers * @hr_timeouts: time out list for active otg fsm timers * @enabled_otg_timer_bits: bits of enabled otg timers * @next_otg_timer: next nearest enabled timer to be expired * @work: work for role changing * @power_lost_work: work for power lost handling * @wq: workqueue thread * @qh_pool: allocation pool for queue heads * @td_pool: allocation pool for transfer descriptors * @gadget: device side representation for peripheral controller * @driver: gadget driver * @resume_state: save the state of gadget suspend from * @hw_ep_max: total number of endpoints supported by hardware * @ci_hw_ep: array of endpoints * @ep0_dir: ep0 direction * @ep0out: pointer to ep0 OUT endpoint * @ep0in: pointer to ep0 IN endpoint * @status: ep0 status request * @setaddr: if we should set the address on status completion * @address: usb address received from the host * @remote_wakeup: host-enabled remote wakeup * @suspended: suspended by host * @test_mode: the selected test mode * @platdata: platform specific information supplied by parent device * @vbus_active: is VBUS active * @ulpi: pointer to ULPI device, if any * @ulpi_ops: ULPI read/write ops for this device * @phy: pointer to PHY, if any * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework * @hcd: pointer to usb_hcd for ehci host driver * @id_event: indicates there is an id event, and handled at ci_otg_work * @b_sess_valid_event: indicates there is a vbus event, and handled * at ci_otg_work * @imx28_write_fix: Freescale imx28 needs swp instruction for writing * @supports_runtime_pm: if runtime pm is supported * @in_lpm: if the core in low power mode * @wakeup_int: if wakeup interrupt occur * @rev: The revision number for controller * @mutex: protect code from concorrent running when doing role switch */ struct ci_hdrc { … }; static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) { … } static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) { … } static inline void ci_role_stop(struct ci_hdrc *ci) { … } static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci) { … } static inline enum ci_role usb_role_to_ci_role(enum usb_role role) { … } /** * hw_read_id_reg: reads from a identification register * @ci: the controller * @offset: offset from the beginning of identification registers region * @mask: bitfield mask * * This function returns register contents */ static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) { … } /** * hw_write_id_reg: writes to a identification register * @ci: the controller * @offset: offset from the beginning of identification registers region * @mask: bitfield mask * @data: new value */ static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask, u32 data) { … } /** * hw_read: reads from a hw register * @ci: the controller * @reg: register index * @mask: bitfield mask * * This function returns register contents */ static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) { … } #ifdef CONFIG_SOC_IMX28 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) { __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); } #else static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) { … } #endif static inline void __hw_write(struct ci_hdrc *ci, u32 val, void __iomem *addr) { … } /** * hw_write: writes to a hw register * @ci: the controller * @reg: register index * @mask: bitfield mask * @data: new value */ static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, u32 data) { … } /** * hw_test_and_clear: tests & clears a hw register * @ci: the controller * @reg: register index * @mask: bitfield mask * * This function returns register contents */ static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) { … } /** * hw_test_and_write: tests & writes a hw register * @ci: the controller * @reg: register index * @mask: bitfield mask * @data: new value * * This function returns register contents */ static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, u32 data) { … } /** * ci_otg_is_fsm_mode: runtime check if otg controller * is in otg fsm mode. * * @ci: chipidea device */ static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci) { … } int ci_ulpi_init(struct ci_hdrc *ci); void ci_ulpi_exit(struct ci_hdrc *ci); int ci_ulpi_resume(struct ci_hdrc *ci); u32 hw_read_intr_enable(struct ci_hdrc *ci); u32 hw_read_intr_status(struct ci_hdrc *ci); int hw_device_reset(struct ci_hdrc *ci); int hw_port_test_set(struct ci_hdrc *ci, u8 mode); u8 hw_port_test_get(struct ci_hdrc *ci); void hw_phymode_configure(struct ci_hdrc *ci); void ci_platform_configure(struct ci_hdrc *ci); void dbg_create_files(struct ci_hdrc *ci); void dbg_remove_files(struct ci_hdrc *ci); #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
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