// SPDX-License-Identifier: GPL-2.0+ /* * PLX NET2272 high/full speed USB device controller * * Copyright (C) 2005-2006 PLX Technology, Inc. * Copyright (C) 2006-2011 Analog Devices, Inc. */ #ifndef __NET2272_H__ #define __NET2272_H__ /* Main Registers */ #define REGADDRPTR … #define REGDATA … #define IRQSTAT0 … #define ENDPOINT_0_INTERRUPT … #define ENDPOINT_A_INTERRUPT … #define ENDPOINT_B_INTERRUPT … #define ENDPOINT_C_INTERRUPT … #define VIRTUALIZED_ENDPOINT_INTERRUPT … #define SETUP_PACKET_INTERRUPT … #define DMA_DONE_INTERRUPT … #define SOF_INTERRUPT … #define IRQSTAT1 … #define CONTROL_STATUS_INTERRUPT … #define VBUS_INTERRUPT … #define SUSPEND_REQUEST_INTERRUPT … #define SUSPEND_REQUEST_CHANGE_INTERRUPT … #define RESUME_INTERRUPT … #define ROOT_PORT_RESET_INTERRUPT … #define RESET_STATUS … #define PAGESEL … #define DMAREQ … #define DMA_ENDPOINT_SELECT … #define DREQ_POLARITY … #define DACK_POLARITY … #define EOT_POLARITY … #define DMA_CONTROL_DACK … #define DMA_REQUEST_ENABLE … #define DMA_REQUEST … #define DMA_BUFFER_VALID … #define SCRATCH … #define IRQENB0 … #define ENDPOINT_0_INTERRUPT_ENABLE … #define ENDPOINT_A_INTERRUPT_ENABLE … #define ENDPOINT_B_INTERRUPT_ENABLE … #define ENDPOINT_C_INTERRUPT_ENABLE … #define VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE … #define SETUP_PACKET_INTERRUPT_ENABLE … #define DMA_DONE_INTERRUPT_ENABLE … #define SOF_INTERRUPT_ENABLE … #define IRQENB1 … #define VBUS_INTERRUPT_ENABLE … #define SUSPEND_REQUEST_INTERRUPT_ENABLE … #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE … #define RESUME_INTERRUPT_ENABLE … #define ROOT_PORT_RESET_INTERRUPT_ENABLE … #define LOCCTL … #define DATA_WIDTH … #define LOCAL_CLOCK_OUTPUT … #define LOCAL_CLOCK_OUTPUT_OFF … #define LOCAL_CLOCK_OUTPUT_3_75MHZ … #define LOCAL_CLOCK_OUTPUT_7_5MHZ … #define LOCAL_CLOCK_OUTPUT_15MHZ … #define LOCAL_CLOCK_OUTPUT_30MHZ … #define LOCAL_CLOCK_OUTPUT_60MHZ … #define DMA_SPLIT_BUS_MODE … #define BYTE_SWAP … #define BUFFER_CONFIGURATION … #define BUFFER_CONFIGURATION_EPA512_EPB512 … #define BUFFER_CONFIGURATION_EPA1024_EPB512 … #define BUFFER_CONFIGURATION_EPA1024_EPB1024 … #define BUFFER_CONFIGURATION_EPA1024DB … #define CHIPREV_LEGACY … #define NET2270_LEGACY_REV … #define LOCCTL1 … #define DMA_MODE … #define SLOW_DREQ … #define FAST_DREQ … #define BURST_MODE … #define DMA_DACK_ENABLE … #define CHIPREV_2272 … #define CHIPREV_NET2272_R1 … #define CHIPREV_NET2272_R1A … /* USB Registers */ #define USBCTL0 … #define IO_WAKEUP_ENABLE … #define USB_DETECT_ENABLE … #define USB_ROOT_PORT_WAKEUP_ENABLE … #define USBCTL1 … #define VBUS_PIN … #define USB_FULL_SPEED … #define USB_HIGH_SPEED … #define GENERATE_RESUME … #define VIRTUAL_ENDPOINT_ENABLE … #define FRAME0 … #define FRAME1 … #define OURADDR … #define FORCE_IMMEDIATE … #define USBDIAG … #define FORCE_TRANSMIT_CRC_ERROR … #define PREVENT_TRANSMIT_BIT_STUFF … #define FORCE_RECEIVE_ERROR … #define FAST_TIMES … #define USBTEST … #define TEST_MODE_SELECT … #define NORMAL_OPERATION … #define XCVRDIAG … #define FORCE_FULL_SPEED … #define FORCE_HIGH_SPEED … #define OPMODE … #define NORMAL_OPERATION … #define NON_DRIVING … #define DISABLE_BITSTUFF_AND_NRZI_ENCODE … #define LINESTATE … #define SE0_STATE … #define J_STATE … #define K_STATE … #define SE1_STATE … #define VIRTOUT0 … #define VIRTOUT1 … #define VIRTIN0 … #define VIRTIN1 … #define SETUP0 … #define SETUP1 … #define SETUP2 … #define SETUP3 … #define SETUP4 … #define SETUP5 … #define SETUP6 … #define SETUP7 … /* Endpoint Registers (Paged via PAGESEL) */ #define EP_DATA … #define EP_STAT0 … #define DATA_IN_TOKEN_INTERRUPT … #define DATA_OUT_TOKEN_INTERRUPT … #define DATA_PACKET_TRANSMITTED_INTERRUPT … #define DATA_PACKET_RECEIVED_INTERRUPT … #define SHORT_PACKET_TRANSFERRED_INTERRUPT … #define NAK_OUT_PACKETS … #define BUFFER_EMPTY … #define BUFFER_FULL … #define EP_STAT1 … #define TIMEOUT … #define USB_OUT_ACK_SENT … #define USB_OUT_NAK_SENT … #define USB_IN_ACK_RCVD … #define USB_IN_NAK_SENT … #define USB_STALL_SENT … #define LOCAL_OUT_ZLP … #define BUFFER_FLUSH … #define EP_TRANSFER0 … #define EP_TRANSFER1 … #define EP_TRANSFER2 … #define EP_IRQENB … #define DATA_IN_TOKEN_INTERRUPT_ENABLE … #define DATA_OUT_TOKEN_INTERRUPT_ENABLE … #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE … #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE … #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE … #define EP_AVAIL0 … #define EP_AVAIL1 … #define EP_RSPCLR … #define EP_RSPSET … #define ENDPOINT_HALT … #define ENDPOINT_TOGGLE … #define NAK_OUT_PACKETS_MODE … #define CONTROL_STATUS_PHASE_HANDSHAKE … #define INTERRUPT_MODE … #define AUTOVALIDATE … #define HIDE_STATUS_PHASE … #define ALT_NAK_OUT_PACKETS … #define EP_MAXPKT0 … #define EP_MAXPKT1 … #define ADDITIONAL_TRANSACTION_OPPORTUNITIES … #define NONE_ADDITIONAL_TRANSACTION … #define ONE_ADDITIONAL_TRANSACTION … #define TWO_ADDITIONAL_TRANSACTION … #define EP_CFG … #define ENDPOINT_NUMBER … #define ENDPOINT_DIRECTION … #define ENDPOINT_TYPE … #define ENDPOINT_ENABLE … #define EP_HBW … #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID … #define DATA0_PID … #define DATA1_PID … #define DATA2_PID … #define MDATA_PID … #define EP_BUFF_STATES … #define BUFFER_A_STATE … #define BUFFER_B_STATE … #define BUFF_FREE … #define BUFF_VALID … #define BUFF_LCL … #define BUFF_USB … /*---------------------------------------------------------------------------*/ #define PCI_DEVICE_ID_RDK1 … /* PCI-RDK EPLD Registers */ #define RDK_EPLD_IO_REGISTER1 … #define RDK_EPLD_USB_RESET … #define RDK_EPLD_USB_POWERDOWN … #define RDK_EPLD_USB_WAKEUP … #define RDK_EPLD_USB_EOT … #define RDK_EPLD_DPPULL … #define RDK_EPLD_IO_REGISTER2 … #define RDK_EPLD_BUSWIDTH … #define RDK_EPLD_USER … #define RDK_EPLD_RESET_INTERRUPT_ENABLE … #define RDK_EPLD_DMA_TIMEOUT_ENABLE … #define RDK_EPLD_STATUS_REGISTER … #define RDK_EPLD_USB_LRESET … #define RDK_EPLD_REVISION_REGISTER … /* PCI-RDK PLX 9054 Registers */ #define INTCSR … #define PCI_INTERRUPT_ENABLE … #define LOCAL_INTERRUPT_INPUT_ENABLE … #define LOCAL_INPUT_INTERRUPT_ACTIVE … #define LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE … #define LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE … #define DMA_CHANNEL_0_INTERRUPT_ACTIVE … #define DMA_CHANNEL_1_INTERRUPT_ACTIVE … #define CNTRL … #define RELOAD_CONFIGURATION_REGISTERS … #define PCI_ADAPTER_SOFTWARE_RESET … #define DMAMODE0 … #define LOCAL_BUS_WIDTH … #define INTERNAL_WAIT_STATES … #define TA_READY_INPUT_ENABLE … #define LOCAL_BURST_ENABLE … #define SCATTER_GATHER_MODE … #define DONE_INTERRUPT_ENABLE … #define LOCAL_ADDRESSING_MODE … #define DEMAND_MODE … #define DMA_EOT_ENABLE … #define FAST_SLOW_TERMINATE_MODE_SELECT … #define DMA_CHANNEL_INTERRUPT_SELECT … #define DMAPADR0 … #define DMALADR0 … #define DMASIZ0 … #define DMADPR0 … #define DESCRIPTOR_LOCATION … #define END_OF_CHAIN … #define INTERRUPT_AFTER_TERMINAL_COUNT … #define DIRECTION_OF_TRANSFER … #define DMACSR0 … #define CHANNEL_ENABLE … #define CHANNEL_START … #define CHANNEL_ABORT … #define CHANNEL_CLEAR_INTERRUPT … #define CHANNEL_DONE … #define DMATHR … #define LBRD1 … #define MEMORY_SPACE_LOCAL_BUS_WIDTH … #define W8_BIT … #define W16_BIT … /* Special OR'ing of INTCSR bits */ #define LOCAL_INTERRUPT_TEST … #define DMA_CHANNEL_0_TEST … #define DMA_CHANNEL_1_TEST … /* EPLD Registers */ #define RDK_EPLD_IO_REGISTER1 … #define RDK_EPLD_USB_RESET … #define RDK_EPLD_USB_POWERDOWN … #define RDK_EPLD_USB_WAKEUP … #define RDK_EPLD_USB_EOT … #define RDK_EPLD_DPPULL … #define RDK_EPLD_IO_REGISTER2 … #define RDK_EPLD_BUSWIDTH … #define RDK_EPLD_USER … #define RDK_EPLD_RESET_INTERRUPT_ENABLE … #define RDK_EPLD_DMA_TIMEOUT_ENABLE … #define RDK_EPLD_STATUS_REGISTER … #define RDK_EPLD_USB_LRESET … #define RDK_EPLD_REVISION_REGISTER … #define EPLD_IO_CONTROL_REGISTER … #define NET2272_RESET … #define BUSWIDTH … #define MPX_MODE … #define USER … #define DMA_TIMEOUT_ENABLE … #define DMA_CTL_DACK … #define EPLD_DMA_ENABLE … #define EPLD_DMA_CONTROL_REGISTER … #define SPLIT_DMA_MODE … #define SPLIT_DMA_DIRECTION … #define SPLIT_DMA_ENABLE … #define SPLIT_DMA_INTERRUPT_ENABLE … #define SPLIT_DMA_INTERRUPT … #define EPLD_DMA_MODE … #define EPLD_DMA_CONTROLLER_ENABLE … #define SPLIT_DMA_ADDRESS_LOW … #define SPLIT_DMA_ADDRESS_HIGH … #define SPLIT_DMA_BYTE_COUNT_LOW … #define SPLIT_DMA_BYTE_COUNT_HIGH … #define EPLD_REVISION_REGISTER … #define SPLIT_DMA_RAM … #define DMA_RAM_SIZE … /*---------------------------------------------------------------------------*/ #define PCI_DEVICE_ID_RDK2 … /* PCI-RDK version 2 registers */ /* Main Control Registers */ #define RDK2_IRQENB … #define RDK2_IRQSTAT … #define PB7 … #define PB6 … #define PB5 … #define PB4 … #define PB3 … #define PB2 … #define PB1 … #define PB0 … #define GP3 … #define GP2 … #define GP1 … #define GP0 … #define DMA_RETRY_ABORT … #define DMA_PAUSE_DONE … #define DMA_ABORT_DONE … #define DMA_OUT_FIFO_TRANSFER_DONE … #define DMA_LOCAL_DONE … #define DMA_PCI_DONE … #define NET2272_PCI_IRQ … #define RDK2_LOCCTLRDK … #define CHIP_RESET … #define SPLIT_DMA … #define MULTIPLEX_MODE … #define BUS_WIDTH … #define RDK2_GPIOCTL … #define GP3_OUT_ENABLE … #define GP2_OUT_ENABLE … #define GP1_OUT_ENABLE … #define GP0_OUT_ENABLE … #define GP3_DATA … #define GP2_DATA … #define GP1_DATA … #define GP0_DATA … #define RDK2_LEDSW … #define LED3 … #define LED2 … #define LED1 … #define LED0 … #define PBUTTON … #define DIPSW … #define RDK2_DIAG … #define RDK2_FAST_TIMES … #define FORCE_PCI_SERR … #define FORCE_PCI_INT … #define RDK2_FPGAREV … /* Dma Control registers */ #define RDK2_DMACTL … #define ADDR_HOLD … #define RETRY_COUNT … #define FIFO_THRESHOLD … #define MEM_WRITE_INVALIDATE … #define READ_MULTIPLE … #define READ_LINE … #define RDK2_DMA_MODE … #define CONTROL_DACK … #define EOT_ENABLE … #define EOT_POLARITY … #define DACK_POLARITY … #define DREQ_POLARITY … #define DMA_ENABLE … #define RDK2_DMASTAT … #define GATHER_COUNT … #define FIFO_COUNT … #define FIFO_FLUSH … #define FIFO_TRANSFER … #define PAUSE_DONE … #define ABORT_DONE … #define DMA_ABORT … #define DMA_START … #define RDK2_DMAPCICOUNT … #define DMA_DIRECTION … #define DMA_PCI_BYTE_COUNT … #define RDK2_DMALOCCOUNT … #define RDK2_DMAADDR … /*---------------------------------------------------------------------------*/ #define REG_INDEXED_THRESHOLD … /* DRIVER DATA STRUCTURES and UTILITIES */ struct net2272_ep { … }; struct net2272 { … }; static void __iomem * net2272_reg_addr(struct net2272 *dev, unsigned int reg) { … } static void net2272_write(struct net2272 *dev, unsigned int reg, u8 value) { … } static u8 net2272_read(struct net2272 *dev, unsigned int reg) { … } static void net2272_ep_write(struct net2272_ep *ep, unsigned int reg, u8 value) { … } static u8 net2272_ep_read(struct net2272_ep *ep, unsigned int reg) { … } static void allow_status(struct net2272_ep *ep) { … } static void set_halt(struct net2272_ep *ep) { … } static void clear_halt(struct net2272_ep *ep) { … } /* count (<= 4) bytes in the next fifo write will be valid */ static void set_fifo_bytecount(struct net2272_ep *ep, unsigned count) { … } struct net2272_request { … }; #endif
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