// SPDX-License-Identifier: GPL-2.0+ /* * linux/drivers/usb/gadget/pxa27x_udc.h * Intel PXA27x on-chip full speed USB device controller * * Inspired by original driver by Frank Becker, David Brownell, and others. * Copyright (C) 2008 Robert Jarzmik */ #ifndef __LINUX_USB_GADGET_PXA27X_H #define __LINUX_USB_GADGET_PXA27X_H #include <linux/types.h> #include <linux/spinlock.h> #include <linux/io.h> #include <linux/usb/otg.h> /* * Register definitions */ /* Offsets */ #define UDCCR … #define UDCICR0 … #define UDCICR1 … #define UDCISR0 … #define UDCISR1 … #define UDCFNR … #define UDCOTGICR … #define UP2OCR … #define UP3OCR … #define UDCCSRn(x) … #define UDCBCRn(x) … #define UDCDRn(x) … #define UDCCRn(x) … #define UDCCR_OEN … #define UDCCR_AALTHNP … #define UDCCR_AHNP … #define UDCCR_BHNP … #define UDCCR_DWRE … #define UDCCR_ACN … #define UDCCR_ACN_S … #define UDCCR_AIN … #define UDCCR_AIN_S … #define UDCCR_AAISN … #define UDCCR_AAISN_S … #define UDCCR_SMAC … #define UDCCR_EMCE … #define UDCCR_UDR … #define UDCCR_UDA … #define UDCCR_UDE … #define UDCICR_INT(n, intr) … #define UDCICR1_IECC … #define UDCICR1_IESOF … #define UDCICR1_IERU … #define UDCICR1_IESU … #define UDCICR1_IERS … #define UDCICR_FIFOERR … #define UDCICR_PKTCOMPL … #define UDCICR_INT_MASK … #define UDCISR_INT(n, intr) … #define UDCISR1_IRCC … #define UDCISR1_IRSOF … #define UDCISR1_IRRU … #define UDCISR1_IRSU … #define UDCISR1_IRRS … #define UDCISR_INT_MASK … #define UDCOTGICR_IESF … #define UDCOTGICR_IEXR … #define UDCOTGICR_IEXF … #define UDCOTGICR_IEVV40R … #define UDCOTGICR_IEVV40F … #define UDCOTGICR_IEVV44R … #define UDCOTGICR_IEVV44F … #define UDCOTGICR_IESVR … #define UDCOTGICR_IESVF … #define UDCOTGICR_IESDR … #define UDCOTGICR_IESDF … #define UDCOTGICR_IEIDR … #define UDCOTGICR_IEIDF … /* Host Port 2 field bits */ #define UP2OCR_CPVEN … #define UP2OCR_CPVPE … /* Transceiver enablers */ #define UP2OCR_DPPDE … #define UP2OCR_DMPDE … #define UP2OCR_DPPUE … #define UP2OCR_DMPUE … #define UP2OCR_DPPUBE … #define UP2OCR_DMPUBE … #define UP2OCR_EXSP … #define UP2OCR_EXSUS … #define UP2OCR_IDON … #define UP2OCR_HXS … #define UP2OCR_HXOE … #define UP2OCR_SEOS … #define UDCCSR0_ACM … #define UDCCSR0_AREN … #define UDCCSR0_SA … #define UDCCSR0_RNE … #define UDCCSR0_FST … #define UDCCSR0_SST … #define UDCCSR0_DME … #define UDCCSR0_FTF … #define UDCCSR0_IPR … #define UDCCSR0_OPC … #define UDCCSR_DPE … #define UDCCSR_FEF … #define UDCCSR_SP … #define UDCCSR_BNE … #define UDCCSR_BNF … #define UDCCSR_FST … #define UDCCSR_SST … #define UDCCSR_DME … #define UDCCSR_TRN … #define UDCCSR_PC … #define UDCCSR_FS … #define UDCCONR_CN … #define UDCCONR_CN_S … #define UDCCONR_IN … #define UDCCONR_IN_S … #define UDCCONR_AISN … #define UDCCONR_AISN_S … #define UDCCONR_EN … #define UDCCONR_EN_S … #define UDCCONR_ET … #define UDCCONR_ET_S … #define UDCCONR_ET_INT … #define UDCCONR_ET_BULK … #define UDCCONR_ET_ISO … #define UDCCONR_ET_NU … #define UDCCONR_ED … #define UDCCONR_MPS … #define UDCCONR_MPS_S … #define UDCCONR_DE … #define UDCCONR_EE … #define UDCCR_MASK_BITS … #define UDCCSR_WR_MASK … #define UDC_FNR_MASK … #define UDC_BCR_MASK … /* * UDCCR = UDC Endpoint Configuration Registers * UDCCSR = UDC Control/Status Register for this EP * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo) * UDCDR = UDC Endpoint Data Register (the fifo) */ #define ofs_UDCCR(ep) … #define ofs_UDCCSR(ep) … #define ofs_UDCBCR(ep) … #define ofs_UDCDR(ep) … /* Register access macros */ #define udc_ep_readl(ep, reg) … #define udc_ep_writel(ep, reg, value) … #define udc_ep_readb(ep, reg) … #define udc_ep_writeb(ep, reg, value) … #define udc_readl(dev, reg) … #define udc_writel(udc, reg, value) … #define UDCCSR_MASK … #define UDCCISR0_EP_MASK … #define UDCCISR1_EP_MASK … #define UDCCSR0_CTRL_REQ_MASK … #define EPIDX(ep) … #define EPADDR(ep) … #define EPXFERTYPE(ep) … #define EPNAME(ep) … #define is_ep0(ep) … #define EPXFERTYPE_is_ISO(ep) … /* * Endpoint definitions * * Once enabled, pxa endpoint configuration is freezed, and cannot change * unless a reset happens or the udc is disabled. * Therefore, we must define all pxa potential endpoint definitions needed for * all gadget and set them up before the udc is enabled. * * As the architecture chosen is fully static, meaning the pxa endpoint * configurations are set up once and for all, we must provide a way to match * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt) * criteria, while the pxa architecture requires that. * * The solution is to define several pxa endpoints matching one usb_ep. Ex: * - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when * the udc talks on (config=3, interface=0, alt=0) * - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when * the udc talks on (config=3, interface=0, alt=1) * - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when * the udc talks on (config=2, interface=0, alt=0) * * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...) */ /* * Endpoint definition helpers */ #define USB_EP_DEF(addr, bname, dir, type, maxpkt, ctype, cdir) … #define USB_EP_BULK(addr, bname, dir, cdir) … #define USB_EP_ISO(addr, bname, dir, cdir) … #define USB_EP_INT(addr, bname, dir, cdir) … #define USB_EP_IN_BULK(n) … #define USB_EP_OUT_BULK(n) … #define USB_EP_IN_ISO(n) … #define USB_EP_OUT_ISO(n) … #define USB_EP_IN_INT(n) … #define USB_EP_CTRL … #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) … #define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) … #define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) … #define PXA_EP_INT(_idx, addr, dir, config, iface, alt) … #define PXA_EP_IN_BULK(i, adr, c, f, a) … #define PXA_EP_OUT_BULK(i, adr, c, f, a) … #define PXA_EP_IN_ISO(i, adr, c, f, a) … #define PXA_EP_OUT_ISO(i, adr, c, f, a) … #define PXA_EP_IN_INT(i, adr, c, f, a) … #define PXA_EP_CTRL … struct pxa27x_udc; struct stats { … }; /** * struct udc_usb_ep - container of each usb_ep structure * @usb_ep: usb endpoint * @desc: usb descriptor, especially type and address * @dev: udc managing this endpoint * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call) */ struct udc_usb_ep { … }; /** * struct pxa_ep - pxa endpoint * @dev: udc device * @queue: requests queue * @lock: lock to pxa_ep data (queues and stats) * @enabled: true when endpoint enabled (not stopped by gadget layer) * @in_handle_ep: number of recursions of handle_ep() function * Prevents deadlocks or infinite recursions of types : * irq->handle_ep()->req_done()->req.complete()->pxa_ep_queue()->handle_ep() * or * pxa_ep_queue()->handle_ep()->req_done()->req.complete()->pxa_ep_queue() * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX) * @name: endpoint name (for trace/debug purpose) * @dir_in: 1 if IN endpoint, 0 if OUT endpoint * @addr: usb endpoint number * @config: configuration in which this endpoint is active * @interface: interface in which this endpoint is active * @alternate: altsetting in which this endpoint is active * @fifo_size: max packet size in the endpoint fifo * @type: endpoint type (bulk, iso, int, ...) * @udccsr_value: save register of UDCCSR0 for suspend/resume * @udccr_value: save register of UDCCR for suspend/resume * @stats: endpoint statistics * * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned * (cares about config/interface/altsetting, thus placing needless limits on * device capability) and full of implementation bugs forcing it to be set up * for use more or less like a pxa255. * * As we define the pxa_ep statically, we must guess all needed pxa_ep for all * gadget which may work with this udc driver. */ struct pxa_ep { … }; /** * struct pxa27x_request - container of each usb_request structure * @req: usb request * @udc_usb_ep: usb endpoint the request was submitted on * @in_use: sanity check if request already queued on an pxa_ep * @queue: linked list of requests, linked on pxa_ep->queue */ struct pxa27x_request { … }; enum ep0_state { … }; static char *ep0_state_name[] = …; #define EP0_STNAME(udc) … #define EP0_FIFO_SIZE … #define BULK_FIFO_SIZE … #define ISO_FIFO_SIZE … #define INT_FIFO_SIZE … struct udc_stats { … }; #define NR_USB_ENDPOINTS … #define NR_PXA_ENDPOINTS … /** * struct pxa_udc - udc structure * @regs: mapped IO space * @irq: udc irq * @clk: udc clock * @usb_gadget: udc gadget structure * @driver: bound gadget (zero, g_ether, g_mass_storage, ...) * @dev: device * @udc_command: machine specific function to activate D+ pullup * @gpiod: gpio descriptor of gpio for D+ pullup (or NULL if none) * @transceiver: external transceiver to handle vbus sense and D+ pullup * @ep0state: control endpoint state machine state * @stats: statistics on udc usage * @udc_usb_ep: array of usb endpoints offered by the gadget * @pxa_ep: array of pxa available endpoints * @enabled: UDC was enabled by a previous udc_enable() * @pullup_on: if pullup resistor connected to D+ pin * @pullup_resume: if pullup resistor should be connected to D+ pin on resume * @config: UDC active configuration * @last_interface: UDC interface of the last SET_INTERFACE host request * @last_alternate: UDC altsetting of the last SET_INTERFACE host request * @udccsr0: save of udccsr0 in case of suspend * @debugfs_state: debugfs entry for "udcstate" * @debugfs_queues: debugfs entry for "queues" * @debugfs_eps: debugfs entry for "epstate" */ struct pxa_udc { … }; #define to_pxa(g) … static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget) { … } /* * Debugging/message support */ #define ep_dbg(ep, fmt, arg...) … #define ep_vdbg(ep, fmt, arg...) … #define ep_err(ep, fmt, arg...) … #define ep_info(ep, fmt, arg...) … #define ep_warn(ep, fmt, arg...) … #endif /* __LINUX_USB_GADGET_PXA27X_H */
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