/************************************************************************** Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sub license, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **************************************************************************/ /* * Authors: * Kevin E. Martin <[email protected]> */ /* I/O register offsets */ #define SRX … #define GRX … #define ARX … #define XRX … #define MRX … /* VGA Color Palette Registers */ #define DACMASK … #define DACSTATE … #define DACRX … #define DACWX … #define DACDATA … /* CRT Controller Registers (CRX) */ #define START_ADDR_HI … #define START_ADDR_LO … #define VERT_SYNC_END … #define EXT_VERT_TOTAL … #define EXT_VERT_DISPLAY … #define EXT_VERT_SYNC_START … #define EXT_VERT_BLANK_START … #define EXT_HORIZ_TOTAL … #define EXT_HORIZ_BLANK … #define EXT_START_ADDR … #define EXT_START_ADDR_ENABLE … #define EXT_OFFSET … #define EXT_START_ADDR_HI … #define INTERLACE_CNTL … #define INTERLACE_ENABLE … #define INTERLACE_DISABLE … /* Miscellaneous Output Register */ #define MSR_R … #define MSR_W … #define IO_ADDR_SELECT … #define MDA_BASE … #define CGA_BASE … /* System Configuration Extension Registers (XRX) */ #define IO_CTNL … #define EXTENDED_ATTR_CNTL … #define EXTENDED_CRTC_CNTL … #define ADDRESS_MAPPING … #define PACKED_MODE_ENABLE … #define LINEAR_MODE_ENABLE … #define PAGE_MAPPING_ENABLE … #define BITBLT_CNTL … #define COLEXP_MODE … #define COLEXP_8BPP … #define COLEXP_16BPP … #define COLEXP_24BPP … #define COLEXP_RESERVED … #define CHIP_RESET … #define BITBLT_STATUS … #define DISPLAY_CNTL … #define VGA_WRAP_MODE … #define VGA_WRAP_AT_256KB … #define VGA_NO_WRAP … #define GUI_MODE … #define STANDARD_VGA_MODE … #define HIRES_MODE … #define DRAM_ROW_TYPE … #define DRAM_ROW_0 … #define DRAM_ROW_0_SDRAM … #define DRAM_ROW_0_EMPTY … #define DRAM_ROW_1 … #define DRAM_ROW_1_SDRAM … #define DRAM_ROW_1_EMPTY … #define DRAM_ROW_CNTL_LO … #define DRAM_CAS_LATENCY … #define DRAM_RAS_TIMING … #define DRAM_RAS_PRECHARGE … #define DRAM_ROW_CNTL_HI … #define DRAM_EXT_CNTL … #define DRAM_REFRESH_RATE … #define DRAM_REFRESH_DISABLE … #define DRAM_REFRESH_60HZ … #define DRAM_REFRESH_FAST_TEST … #define DRAM_REFRESH_RESERVED … #define DRAM_TIMING … #define DRAM_ROW_BNDRY_0 … #define DRAM_ROW_BNDRY_1 … #define DPMS_SYNC_SELECT … #define VSYNC_CNTL … #define VSYNC_ON … #define VSYNC_OFF … #define HSYNC_CNTL … #define HSYNC_ON … #define HSYNC_OFF … #define PIXPIPE_CONFIG_0 … #define DAC_8_BIT … #define DAC_6_BIT … #define HW_CURSOR_ENABLE … #define EXTENDED_PALETTE … #define PIXPIPE_CONFIG_1 … #define DISPLAY_COLOR_MODE … #define DISPLAY_VGA_MODE … #define DISPLAY_8BPP_MODE … #define DISPLAY_15BPP_MODE … #define DISPLAY_16BPP_MODE … #define DISPLAY_24BPP_MODE … #define DISPLAY_32BPP_MODE … #define PIXPIPE_CONFIG_2 … #define DISPLAY_GAMMA_ENABLE … #define DISPLAY_GAMMA_DISABLE … #define OVERLAY_GAMMA_ENABLE … #define OVERLAY_GAMMA_DISABLE … #define CURSOR_CONTROL … #define CURSOR_ORIGIN_SCREEN … #define CURSOR_ORIGIN_DISPLAY … #define CURSOR_MODE … #define CURSOR_MODE_DISABLE … #define CURSOR_MODE_32_4C_AX … #define CURSOR_MODE_128_2C … #define CURSOR_MODE_128_1C … #define CURSOR_MODE_64_3C … #define CURSOR_MODE_64_4C_AX … #define CURSOR_MODE_64_4C … #define CURSOR_MODE_RESERVED … #define CURSOR_BASEADDR_LO … #define CURSOR_BASEADDR_HI … #define CURSOR_X_LO … #define CURSOR_X_HI … #define CURSOR_X_POS … #define CURSOR_X_NEG … #define CURSOR_Y_LO … #define CURSOR_Y_HI … #define CURSOR_Y_POS … #define CURSOR_Y_NEG … #define VCLK2_VCO_M … #define VCLK2_VCO_N … #define VCLK2_VCO_MN_MSBS … #define VCO_N_MSBS … #define VCO_M_MSBS … #define VCLK2_VCO_DIV_SEL … #define POST_DIV_SELECT … #define POST_DIV_1 … #define POST_DIV_2 … #define POST_DIV_4 … #define POST_DIV_8 … #define POST_DIV_16 … #define POST_DIV_32 … #define VCO_LOOP_DIV_BY_4M … #define VCO_LOOP_DIV_BY_16M … #define REF_CLK_DIV_BY_5 … #define REF_DIV_4 … #define REF_DIV_1 … #define PLL_CNTL … #define PLL_MEMCLK_SEL … #define PLL_MEMCLK__66667KHZ … #define PLL_MEMCLK__75000KHZ … #define PLL_MEMCLK__88889KHZ … #define PLL_MEMCLK_100000KHZ … /* Multimedia Extension Registers (MRX) */ #define ACQ_CNTL_1 … #define ACQ_CNTL_2 … #define FRAME_CAP_MODE … #define CONT_CAP_MODE … #define SINGLE_CAP_MODE … #define ACQ_CNTL_3 … #define COL_KEY_CNTL_1 … #define BLANK_DISP_OVERLAY … /* FIFOs */ #define LP_FIFO … #define HP_FIFO … #define INSTPNT … #define LP_FIFO_COUNT … #define HP_FIFO_COUNT … /* FIFO Commands */ #define CLIENT … #define CLIENT_2D … /* Command Parser Mode Register */ #define COMPARS … #define TWO_D_INST_DISABLE … #define THREE_D_INST_DISABLE … #define STATE_VAR_UPDATE_DISABLE … #define PAL_STIP_DISABLE … /* Interrupt Control Registers */ #define IER … #define IIR … #define IMR … #define ISR … #define VMIINTB_EVENT … #define GPIO4_INT … #define DISP_FLIP_EVENT … #define DVD_PORT_DMA … #define DISP_VBLANK … #define FIFO_EMPTY_DMA_DONE … #define INST_PARSER_ERROR … #define USER_DEFINED … #define BREAKPOINT … #define DISP_HORIZ_COUNT … #define DISP_VSYNC … #define CAPTURE_HORIZ_COUNT … #define CAPTURE_VSYNC … #define THREE_D_PIPE_FLUSHED … /* FIFO Watermark and Burst Length Control Register */ #define FWATER_BLC … #define LMI_BURST_LENGTH … #define LMI_FIFO_WATERMARK … #define AGP_BURST_LENGTH … #define AGP_FIFO_WATERMARK … /* BitBLT Registers */ #define SRC_DST_PITCH … #define DST_PITCH … #define SRC_PITCH … #define COLEXP_BG_COLOR … #define COLEXP_FG_COLOR … #define MONO_SRC_CNTL … #define MONO_USE_COLEXP … #define MONO_USE_SRCEXP … #define MONO_DATA_ALIGN … #define MONO_BIT_ALIGN … #define MONO_BYTE_ALIGN … #define MONO_WORD_ALIGN … #define MONO_DWORD_ALIGN … #define MONO_QWORD_ALIGN … #define MONO_SRC_INIT_DSCRD … #define MONO_SRC_RIGHT_CLIP … #define MONO_SRC_LEFT_CLIP … #define BITBLT_CONTROL … #define BLTR_STATUS … #define DYN_DEPTH … #define DYN_DEPTH_8BPP … #define DYN_DEPTH_16BPP … #define DYN_DEPTH_24BPP … #define DYN_DEPTH_32BPP … #define DYN_DEPTH_ENABLE … #define PAT_VERT_ALIGN … #define SOLID_PAT_SELECT … #define PAT_IS_IN_COLOR … #define PAT_IS_MONO … #define MONO_PAT_TRANSP … #define COLOR_TRANSP_ROP … #define COLOR_TRANSP_DST … #define COLOR_TRANSP_EQ … #define COLOR_TRANSP_NOT_EQ … #define COLOR_TRANSP_ENABLE … #define MONO_SRC_TRANSP … #define SRC_IS_IN_COLOR … #define SRC_IS_MONO … #define SRC_USE_SRC_ADDR … #define SRC_USE_BLTDATA … #define BLT_TOP_TO_BOT … #define BLT_BOT_TO_TOP … #define BLT_LEFT_TO_RIGHT … #define BLT_RIGHT_TO_LEFT … #define BLT_ROP … #define BLT_PAT_ADDR … #define BLT_SRC_ADDR … #define BLT_DST_ADDR … #define BLT_DST_H_W … #define BLT_DST_HEIGHT … #define BLT_DST_WIDTH … #define SRCEXP_BG_COLOR … #define SRCEXP_FG_COLOR … #define BLTDATA …
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