/* SPDX-License-Identifier: GPL-2.0-only */ /* * Definitions for the registers, addresses, and platform data of the * DS1685/DS1687-series RTC chips. * * This Driver also works for the DS17X85/DS17X87 RTC chips. Functionally * similar to the DS1685/DS1687, they support a few extra features which * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC * write counter. * * Copyright (C) 2011-2014 Joshua Kinard <[email protected]>. * Copyright (C) 2009 Matthias Fuchs <[email protected]>. * * References: * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. * Application Note 90, Using the Multiplex Bus RTC Extended Features. */ #ifndef _LINUX_RTC_DS1685_H_ #define _LINUX_RTC_DS1685_H_ #include <linux/rtc.h> #include <linux/platform_device.h> #include <linux/workqueue.h> /** * struct ds1685_priv - DS1685 private data structure. * @dev: pointer to the rtc_device structure. * @regs: iomapped base address pointer of the RTC registers. * @regstep: padding/step size between registers (optional). * @baseaddr: base address of the RTC device. * @size: resource size. * @lock: private lock variable for spin locking/unlocking. * @work: private workqueue. * @irq: IRQ number assigned to the RTC device. * @prepare_poweroff: pointer to platform pre-poweroff function. * @wake_alarm: pointer to platform wake alarm function. * @post_ram_clear: pointer to platform post ram-clear function. */ struct ds1685_priv { … }; /** * struct ds1685_rtc_platform_data - platform data structure. * @plat_prepare_poweroff: platform-specific pre-poweroff function. * @plat_wake_alarm: platform-specific wake alarm function. * @plat_post_ram_clear: platform-specific post ram-clear function. * * If your platform needs to use a custom padding/step size between * registers, or uses one or more of the extended interrupts and needs special * handling, then include this header file in your platform definition and * set regstep and the plat_* pointers as appropriate. */ struct ds1685_rtc_platform_data { … }; /* * Time Registers. */ #define RTC_SECS … #define RTC_SECS_ALARM … #define RTC_MINS … #define RTC_MINS_ALARM … #define RTC_HRS … #define RTC_HRS_ALARM … #define RTC_WDAY … #define RTC_MDAY … #define RTC_MONTH … #define RTC_YEAR … #define RTC_CENTURY … #define RTC_MDAY_ALARM … /* * Bit masks for the Time registers in BCD Mode (DM = 0). */ #define RTC_SECS_BCD_MASK … #define RTC_MINS_BCD_MASK … #define RTC_HRS_12_BCD_MASK … #define RTC_HRS_24_BCD_MASK … #define RTC_MDAY_BCD_MASK … #define RTC_MONTH_BCD_MASK … #define RTC_YEAR_BCD_MASK … /* * Bit masks for the Time registers in BIN Mode (DM = 1). */ #define RTC_SECS_BIN_MASK … #define RTC_MINS_BIN_MASK … #define RTC_HRS_12_BIN_MASK … #define RTC_HRS_24_BIN_MASK … #define RTC_MDAY_BIN_MASK … #define RTC_MONTH_BIN_MASK … #define RTC_YEAR_BIN_MASK … /* * Bit masks common for the Time registers in BCD or BIN Mode. */ #define RTC_WDAY_MASK … #define RTC_CENTURY_MASK … #define RTC_MDAY_ALARM_MASK … #define RTC_HRS_AMPM_MASK … /* * Control Registers. */ #define RTC_CTRL_A … #define RTC_CTRL_B … #define RTC_CTRL_C … #define RTC_CTRL_D … #define RTC_EXT_CTRL_4A … #define RTC_EXT_CTRL_4B … /* * Bit names in Control Register A. */ #define RTC_CTRL_A_UIP … #define RTC_CTRL_A_DV2 … #define RTC_CTRL_A_DV1 … #define RTC_CTRL_A_DV0 … #define RTC_CTRL_A_RS2 … #define RTC_CTRL_A_RS3 … #define RTC_CTRL_A_RS1 … #define RTC_CTRL_A_RS0 … #define RTC_CTRL_A_RS_MASK … /* * Bit names in Control Register B. */ #define RTC_CTRL_B_SET … #define RTC_CTRL_B_PIE … #define RTC_CTRL_B_AIE … #define RTC_CTRL_B_UIE … #define RTC_CTRL_B_SQWE … #define RTC_CTRL_B_DM … #define RTC_CTRL_B_2412 … #define RTC_CTRL_B_DSE … #define RTC_CTRL_B_PAU_MASK … /* * Bit names in Control Register C. * * BIT(0), BIT(1), BIT(2), & BIT(3) are unused, always return 0, and cannot * be written to. */ #define RTC_CTRL_C_IRQF … #define RTC_CTRL_C_PF … #define RTC_CTRL_C_AF … #define RTC_CTRL_C_UF … #define RTC_CTRL_C_PAU_MASK … /* * Bit names in Control Register D. * * BIT(0) through BIT(6) are unused, always return 0, and cannot * be written to. */ #define RTC_CTRL_D_VRT … /* * Bit names in Extended Control Register 4A. * * On the DS1685/DS1687/DS1689/DS1693, BIT(4) and BIT(5) are reserved for * future use. They can be read from and written to, but have no effect * on the RTC's operation. * * On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows * access to the extended NV-SRAM by automatically incrementing the address * register when they are read from or written to. */ #define RTC_CTRL_4A_VRT2 … #define RTC_CTRL_4A_INCR … #define RTC_CTRL_4A_PAB … #define RTC_CTRL_4A_RF … #define RTC_CTRL_4A_WF … #define RTC_CTRL_4A_KF … #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) #define RTC_CTRL_4A_BME … #endif #define RTC_CTRL_4A_RWK_MASK … /* * Bit names in Extended Control Register 4B. */ #define RTC_CTRL_4B_ABE … #define RTC_CTRL_4B_E32K … #define RTC_CTRL_4B_CS … #define RTC_CTRL_4B_RCE … #define RTC_CTRL_4B_PRS … #define RTC_CTRL_4B_RIE … #define RTC_CTRL_4B_WIE … #define RTC_CTRL_4B_KSE … #define RTC_CTRL_4B_RWK_MASK … /* * Misc register names in Bank 1. * * The DV0 bit in Control Register A must be set to 1 for these registers * to become available, including Extended Control Registers 4A & 4B. */ #define RTC_BANK1_SSN_MODEL … #define RTC_BANK1_SSN_BYTE_1 … #define RTC_BANK1_SSN_BYTE_2 … #define RTC_BANK1_SSN_BYTE_3 … #define RTC_BANK1_SSN_BYTE_4 … #define RTC_BANK1_SSN_BYTE_5 … #define RTC_BANK1_SSN_BYTE_6 … #define RTC_BANK1_SSN_CRC … #define RTC_BANK1_RAM_DATA_PORT … /* * Model-specific registers in Bank 1. * * The addresses below differ depending on the model of the RTC chip * selected in the kernel configuration. Not all of these features are * supported in the main driver at present. * * DS1685/DS1687 - Extended NV-SRAM address (LSB only). * DS1689/DS1693 - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N. * DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter. */ #if defined(CONFIG_RTC_DRV_DS1685) #define RTC_BANK1_RAM_ADDR … #elif defined(CONFIG_RTC_DRV_DS1689) #define RTC_BANK1_VCC_CTR_LSB … #define RTC_BANK1_VCC_CTR_MSB … #define RTC_BANK1_VBAT_CTR_LSB … #define RTC_BANK1_VBAT_CTR_MSB … #define RTC_BANK1_PWR_CTR_LSB … #define RTC_BANK1_PWR_CTR_MSB … #define RTC_BANK1_UNIQ_SN … #else /* DS17x85/DS17x87 */ #define RTC_BANK1_RAM_ADDR_LSB … #define RTC_BANK1_RAM_ADDR_MSB … #define RTC_BANK1_WRITE_CTR … #endif /* * Model numbers. * * The DS1688/DS1691 and DS1689/DS1693 chips share the same model number * and the manual doesn't indicate any major differences. As such, they * are regarded as the same chip in this driver. */ #define RTC_MODEL_DS1685 … #define RTC_MODEL_DS17285 … #define RTC_MODEL_DS1689 … #define RTC_MODEL_DS17485 … #define RTC_MODEL_DS17885 … /* * Periodic Interrupt Rates / Square-Wave Output Frequency * * Periodic rates are selected by setting the RS3-RS0 bits in Control * Register A and enabled via either the E32K bit in Extended Control * Register 4B or the SQWE bit in Control Register B. * * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz * on the SQW pin of the RTC chip. While there are 16 possible selections, * the 1-of-16 decoder is only able to divide the base 32768Hz signal into 13 * smaller frequencies. The values 0x01 and 0x02 are not used and are * synonymous with 0x08 and 0x09, respectively. * * When E32K is set to a logic 1, periodic interrupts are disabled and reading * /dev/rtc will return -EINVAL. This also applies if the periodic interrupt * frequency is set to 0Hz. * * Not currently used by the rtc-ds1685 driver because the RTC core removed * support for hardware-generated periodic-interrupts in favour of * hrtimer-generated interrupts. But these defines are kept around for use * in userland, as documentation to the hardware, and possible future use if * hardware-generated periodic interrupts are ever added back. */ /* E32K RS3 RS2 RS1 RS0 */ #define RTC_SQW_8192HZ … #define RTC_SQW_4096HZ … #define RTC_SQW_2048HZ … #define RTC_SQW_1024HZ … #define RTC_SQW_512HZ … #define RTC_SQW_256HZ … #define RTC_SQW_128HZ … #define RTC_SQW_64HZ … #define RTC_SQW_32HZ … #define RTC_SQW_16HZ … #define RTC_SQW_8HZ … #define RTC_SQW_4HZ … #define RTC_SQW_2HZ … #define RTC_SQW_0HZ … #define RTC_SQW_32768HZ … #define RTC_MAX_USER_FREQ … /* * NVRAM data & addresses: * - 50 bytes of NVRAM are available just past the clock registers. * - 64 additional bytes are available in Bank0. * * Extended, battery-backed NV-SRAM: * - DS1685/DS1687 - 128 bytes. * - DS1689/DS1693 - 0 bytes. * - DS17285/DS17287 - 2048 bytes. * - DS17485/DS17487 - 4096 bytes. * - DS17885/DS17887 - 8192 bytes. */ #define NVRAM_TIME_BASE … #define NVRAM_BANK0_BASE … #define NVRAM_SZ_TIME … #define NVRAM_SZ_BANK0 … #if defined(CONFIG_RTC_DRV_DS1685) #define NVRAM_SZ_EXTND … #elif defined(CONFIG_RTC_DRV_DS1689) #define NVRAM_SZ_EXTND … #elif defined(CONFIG_RTC_DRV_DS17285) #define NVRAM_SZ_EXTND … #elif defined(CONFIG_RTC_DRV_DS17485) #define NVRAM_SZ_EXTND … #elif defined(CONFIG_RTC_DRV_DS17885) #define NVRAM_SZ_EXTND … #endif #define NVRAM_TOTAL_SZ_BANK0 … #define NVRAM_TOTAL_SZ … /* * Function Prototypes. */ extern void __noreturn ds1685_rtc_poweroff(struct platform_device *pdev); #endif /* _LINUX_RTC_DS1685_H_ */
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