// SPDX-License-Identifier: GPL-2.0-or-later /* * I2C bus driver for the Cadence I2C controller. * * Copyright (C) 2009 - 2014 Xilinx, Inc. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/pm_runtime.h> #include <linux/pinctrl/consumer.h> #include <linux/reset.h> /* Register offsets for the I2C device. */ #define CDNS_I2C_CR_OFFSET … #define CDNS_I2C_SR_OFFSET … #define CDNS_I2C_ADDR_OFFSET … #define CDNS_I2C_DATA_OFFSET … #define CDNS_I2C_ISR_OFFSET … #define CDNS_I2C_XFER_SIZE_OFFSET … #define CDNS_I2C_TIME_OUT_OFFSET … #define CDNS_I2C_IMR_OFFSET … #define CDNS_I2C_IER_OFFSET … #define CDNS_I2C_IDR_OFFSET … /* Control Register Bit mask definitions */ #define CDNS_I2C_CR_HOLD … #define CDNS_I2C_CR_ACK_EN … #define CDNS_I2C_CR_NEA … #define CDNS_I2C_CR_MS … /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ #define CDNS_I2C_CR_RW … /* 1 = Auto init FIFO to zeroes */ #define CDNS_I2C_CR_CLR_FIFO … #define CDNS_I2C_CR_DIVA_SHIFT … #define CDNS_I2C_CR_DIVA_MASK … #define CDNS_I2C_CR_DIVB_SHIFT … #define CDNS_I2C_CR_DIVB_MASK … #define CDNS_I2C_CR_MASTER_EN_MASK … #define CDNS_I2C_CR_SLAVE_EN_MASK … /* Status Register Bit mask definitions */ #define CDNS_I2C_SR_BA … #define CDNS_I2C_SR_TXDV … #define CDNS_I2C_SR_RXDV … #define CDNS_I2C_SR_RXRW … /* * I2C Address Register Bit mask definitions * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] * bits. A write access to this register always initiates a transfer if the I2C * is in master mode. */ #define CDNS_I2C_ADDR_MASK … /* * I2C Interrupt Registers Bit mask definitions * All the four interrupt registers (Status/Mask/Enable/Disable) have the same * bit definitions. */ #define CDNS_I2C_IXR_ARB_LOST … #define CDNS_I2C_IXR_RX_UNF … #define CDNS_I2C_IXR_TX_OVF … #define CDNS_I2C_IXR_RX_OVF … #define CDNS_I2C_IXR_SLV_RDY … #define CDNS_I2C_IXR_TO … #define CDNS_I2C_IXR_NACK … #define CDNS_I2C_IXR_DATA … #define CDNS_I2C_IXR_COMP … #define CDNS_I2C_IXR_ALL_INTR_MASK … #define CDNS_I2C_IXR_ERR_INTR_MASK … #define CDNS_I2C_ENABLED_INTR_MASK … #define CDNS_I2C_IXR_SLAVE_INTR_MASK … #define CDNS_I2C_TIMEOUT … /* timeout for pm runtime autosuspend */ #define CNDS_I2C_PM_TIMEOUT … #define CDNS_I2C_FIFO_DEPTH_DEFAULT … #define CDNS_I2C_MAX_TRANSFER_SIZE … /* Transfer size in multiples of data interrupt depth */ #define CDNS_I2C_TRANSFER_SIZE(max) … #define DRIVER_NAME … #define CDNS_I2C_DIVA_MAX … #define CDNS_I2C_DIVB_MAX … #define CDNS_I2C_TIMEOUT_MAX … #define CDNS_I2C_BROKEN_HOLD_BIT … #define CDNS_I2C_POLL_US … #define CDNS_I2C_TIMEOUT_US … #define cdns_i2c_readreg(offset) … #define cdns_i2c_writereg(val, offset) … #if IS_ENABLED(CONFIG_I2C_SLAVE) /** * enum cdns_i2c_mode - I2C Controller current operating mode * * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode */ enum cdns_i2c_mode { … }; /** * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode * * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master */ enum cdns_i2c_slave_state { … }; #endif /** * struct cdns_i2c - I2C device private data structure * * @dev: Pointer to device structure * @membase: Base address of the I2C device * @adap: I2C adapter instance * @p_msg: Message pointer * @err_status: Error status in Interrupt Status Register * @xfer_done: Transfer complete status * @p_send_buf: Pointer to transmit buffer * @p_recv_buf: Pointer to receive buffer * @send_count: Number of bytes still expected to send * @recv_count: Number of bytes still expected to receive * @curr_recv_count: Number of bytes to be received in current transfer * @input_clk: Input clock to I2C controller * @i2c_clk: Maximum I2C clock speed * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit * @clk: Pointer to struct clk * @clk_rate_change_nb: Notifier block for clock rate changes * @reset: Reset control for the device * @quirks: flag for broken hold bit usage in r1p10 * @ctrl_reg: Cached value of the control register. * @rinfo: I2C GPIO recovery information * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register * @slave: Registered slave instance. * @dev_mode: I2C operating role(master/slave). * @slave_state: I2C Slave state(idle/read/write). * @fifo_depth: The depth of the transfer FIFO * @transfer_size: The maximum number of bytes in one transfer */ struct cdns_i2c { … }; struct cdns_platform_data { … }; #define to_cdns_i2c(_nb) … /** * cdns_i2c_clear_bus_hold - Clear bus hold bit * @id: Pointer to driver data struct * * Helper to clear the controller's bus hold bit. */ static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) { … } static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) { … } #if IS_ENABLED(CONFIG_I2C_SLAVE) static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) { … } static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) { … } static void cdns_i2c_slave_send_data(struct cdns_i2c *id) { … } /** * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role * @ptr: Pointer to I2C device private data * * This function handles the data interrupt and transfer complete interrupt of * the I2C device in slave role. * * Return: IRQ_HANDLED always */ static irqreturn_t cdns_i2c_slave_isr(void *ptr) { … } #endif /** * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role * @ptr: Pointer to I2C device private data * * This function handles the data interrupt, transfer complete interrupt and * the error interrupts of the I2C device in master role. * * Return: IRQ_HANDLED always */ static irqreturn_t cdns_i2c_master_isr(void *ptr) { … } /** * cdns_i2c_isr - Interrupt handler for the I2C device * @irq: irq number for the I2C device * @ptr: void pointer to cdns_i2c structure * * This function passes the control to slave/master based on current role of * i2c controller. * * Return: IRQ_HANDLED always */ static irqreturn_t cdns_i2c_isr(int irq, void *ptr) { … } /** * cdns_i2c_mrecv - Prepare and start a master receive operation * @id: pointer to the i2c device structure */ static void cdns_i2c_mrecv(struct cdns_i2c *id) { … } /** * cdns_i2c_msend - Prepare and start a master send operation * @id: pointer to the i2c device */ static void cdns_i2c_msend(struct cdns_i2c *id) { … } /** * cdns_i2c_master_reset - Reset the interface * @adap: pointer to the i2c adapter driver instance * * This function cleanup the fifos, clear the hold bit and status * and disable the interrupts. */ static void cdns_i2c_master_reset(struct i2c_adapter *adap) { … } static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, struct i2c_adapter *adap) { … } /** * cdns_i2c_master_xfer - The main i2c transfer function * @adap: pointer to the i2c adapter driver instance * @msgs: pointer to the i2c message structure * @num: the number of messages to transfer * * Initiates the send/recv activity based on the transfer message received. * * Return: number of msgs processed on success, negative error otherwise */ static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { … } /** * cdns_i2c_func - Returns the supported features of the I2C driver * @adap: pointer to the i2c adapter structure * * Return: 32 bit value, each bit corresponding to a feature */ static u32 cdns_i2c_func(struct i2c_adapter *adap) { … } #if IS_ENABLED(CONFIG_I2C_SLAVE) static int cdns_reg_slave(struct i2c_client *slave) { … } static int cdns_unreg_slave(struct i2c_client *slave) { … } #endif static const struct i2c_algorithm cdns_i2c_algo = …; /** * cdns_i2c_calc_divs - Calculate clock dividers * @f: I2C clock frequency * @input_clk: Input clock frequency * @a: First divider (return value) * @b: Second divider (return value) * * f is used as input and output variable. As input it is used as target I2C * frequency. On function exit f holds the actually resulting I2C frequency. * * Return: 0 on success, negative errno otherwise. */ static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, unsigned int *a, unsigned int *b) { … } /** * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device * @clk_in: I2C clock input frequency in Hz * @id: Pointer to the I2C device structure * * The device must be idle rather than busy transferring data before setting * these device options. * The data rate is set by values in the control register. * The formula for determining the correct register values is * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) * See the hardware data sheet for a full explanation of setting the serial * clock rate. The clock can not be faster than the input clock divide by 22. * The two most common clock rates are 100KHz and 400KHz. * * Return: 0 on success, negative error otherwise */ static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) { … } /** * cdns_i2c_clk_notifier_cb - Clock rate change callback * @nb: Pointer to notifier block * @event: Notification reason * @data: Pointer to notification data object * * This function is called when the cdns_i2c input clock frequency changes. * The callback checks whether a valid bus frequency can be generated after the * change. If so, the change is acknowledged, otherwise the change is aborted. * New dividers are written to the HW in the pre- or post change notification * depending on the scaling direction. * * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK * to acknowledge the change, NOTIFY_DONE if the notification is * considered irrelevant. */ static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long event, void *data) { … } /** * cdns_i2c_runtime_suspend - Runtime suspend method for the driver * @dev: Address of the platform_device structure * * Put the driver into low power mode. * * Return: 0 always */ static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) { … } static int __maybe_unused cdns_i2c_suspend(struct device *dev) { … } /** * cdns_i2c_init - Controller initialisation * @id: Device private data structure * * Initialise the i2c controller. * */ static void cdns_i2c_init(struct cdns_i2c *id) { … } /** * cdns_i2c_runtime_resume - Runtime resume * @dev: Address of the platform_device structure * * Runtime resume callback. * * Return: 0 on success and error value on error */ static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) { … } static int __maybe_unused cdns_i2c_resume(struct device *dev) { … } static const struct dev_pm_ops cdns_i2c_dev_pm_ops = …; static const struct cdns_platform_data r1p10_i2c_def = …; static const struct of_device_id cdns_i2c_of_match[] = …; MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); /** * cdns_i2c_detect_transfer_size - Detect the maximum transfer size supported * @id: Device private data structure * * Detect the maximum transfer size that is supported by this instance of the * Cadence I2C controller. */ static void cdns_i2c_detect_transfer_size(struct cdns_i2c *id) { … } /** * cdns_i2c_probe - Platform registration call * @pdev: Handle to the platform device structure * * This function does all the memory allocation and registration for the i2c * device. User can modify the address mode to 10 bit address mode using the * ioctl call with option I2C_TENBIT. * * Return: 0 on success, negative error otherwise */ static int cdns_i2c_probe(struct platform_device *pdev) { … } /** * cdns_i2c_remove - Unregister the device after releasing the resources * @pdev: Handle to the platform device structure * * This function frees all the resources allocated to the device. * * Return: 0 always */ static void cdns_i2c_remove(struct platform_device *pdev) { … } static struct platform_driver cdns_i2c_drv = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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