/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Synopsys DesignWare I2C adapter driver. * * Based on the TI DAVINCI I2C adapter driver. * * Copyright (C) 2006 Texas Instruments. * Copyright (C) 2007 MontaVista Software Inc. * Copyright (C) 2009 Provigent Ltd. */ #include <linux/bits.h> #include <linux/compiler_types.h> #include <linux/completion.h> #include <linux/dev_printk.h> #include <linux/errno.h> #include <linux/i2c.h> #include <linux/regmap.h> #include <linux/types.h> #define DW_IC_DEFAULT_FUNCTIONALITY … #define DW_IC_CON_MASTER … #define DW_IC_CON_SPEED_STD … #define DW_IC_CON_SPEED_FAST … #define DW_IC_CON_SPEED_HIGH … #define DW_IC_CON_SPEED_MASK … #define DW_IC_CON_10BITADDR_SLAVE … #define DW_IC_CON_10BITADDR_MASTER … #define DW_IC_CON_RESTART_EN … #define DW_IC_CON_SLAVE_DISABLE … #define DW_IC_CON_STOP_DET_IFADDRESSED … #define DW_IC_CON_TX_EMPTY_CTRL … #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL … #define DW_IC_CON_BUS_CLEAR_CTRL … #define DW_IC_DATA_CMD_DAT … #define DW_IC_DATA_CMD_FIRST_DATA_BYTE … /* * Registers offset */ #define DW_IC_CON … #define DW_IC_TAR … #define DW_IC_SAR … #define DW_IC_DATA_CMD … #define DW_IC_SS_SCL_HCNT … #define DW_IC_SS_SCL_LCNT … #define DW_IC_FS_SCL_HCNT … #define DW_IC_FS_SCL_LCNT … #define DW_IC_HS_SCL_HCNT … #define DW_IC_HS_SCL_LCNT … #define DW_IC_INTR_STAT … #define DW_IC_INTR_MASK … #define DW_IC_RAW_INTR_STAT … #define DW_IC_RX_TL … #define DW_IC_TX_TL … #define DW_IC_CLR_INTR … #define DW_IC_CLR_RX_UNDER … #define DW_IC_CLR_RX_OVER … #define DW_IC_CLR_TX_OVER … #define DW_IC_CLR_RD_REQ … #define DW_IC_CLR_TX_ABRT … #define DW_IC_CLR_RX_DONE … #define DW_IC_CLR_ACTIVITY … #define DW_IC_CLR_STOP_DET … #define DW_IC_CLR_START_DET … #define DW_IC_CLR_GEN_CALL … #define DW_IC_ENABLE … #define DW_IC_STATUS … #define DW_IC_TXFLR … #define DW_IC_RXFLR … #define DW_IC_SDA_HOLD … #define DW_IC_TX_ABRT_SOURCE … #define DW_IC_ENABLE_STATUS … #define DW_IC_CLR_RESTART_DET … #define DW_IC_COMP_PARAM_1 … #define DW_IC_COMP_VERSION … #define DW_IC_SDA_HOLD_MIN_VERS … #define DW_IC_COMP_TYPE … #define DW_IC_COMP_TYPE_VALUE … #define DW_IC_INTR_RX_UNDER … #define DW_IC_INTR_RX_OVER … #define DW_IC_INTR_RX_FULL … #define DW_IC_INTR_TX_OVER … #define DW_IC_INTR_TX_EMPTY … #define DW_IC_INTR_RD_REQ … #define DW_IC_INTR_TX_ABRT … #define DW_IC_INTR_RX_DONE … #define DW_IC_INTR_ACTIVITY … #define DW_IC_INTR_STOP_DET … #define DW_IC_INTR_START_DET … #define DW_IC_INTR_GEN_CALL … #define DW_IC_INTR_RESTART_DET … #define DW_IC_INTR_MST_ON_HOLD … #define DW_IC_INTR_DEFAULT_MASK … #define DW_IC_INTR_MASTER_MASK … #define DW_IC_INTR_SLAVE_MASK … #define DW_IC_ENABLE_ABORT … #define DW_IC_STATUS_ACTIVITY … #define DW_IC_STATUS_TFE … #define DW_IC_STATUS_RFNE … #define DW_IC_STATUS_MASTER_ACTIVITY … #define DW_IC_STATUS_SLAVE_ACTIVITY … #define DW_IC_SDA_HOLD_RX_SHIFT … #define DW_IC_SDA_HOLD_RX_MASK … #define DW_IC_ERR_TX_ABRT … #define DW_IC_TAR_10BITADDR_MASTER … #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH … #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK … /* * Sofware status flags */ #define STATUS_ACTIVE … #define STATUS_WRITE_IN_PROGRESS … #define STATUS_READ_IN_PROGRESS … #define STATUS_MASK … /* * operation modes */ #define DW_IC_MASTER … #define DW_IC_SLAVE … /* * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register * * Only expected abort codes are listed here * refer to the datasheet for the full list */ #define ABRT_7B_ADDR_NOACK … #define ABRT_10ADDR1_NOACK … #define ABRT_10ADDR2_NOACK … #define ABRT_TXDATA_NOACK … #define ABRT_GCALL_NOACK … #define ABRT_GCALL_READ … #define ABRT_SBYTE_ACKDET … #define ABRT_SBYTE_NORSTRT … #define ABRT_10B_RD_NORSTRT … #define ABRT_MASTER_DIS … #define ARB_LOST … #define ABRT_SLAVE_FLUSH_TXFIFO … #define ABRT_SLAVE_ARBLOST … #define ABRT_SLAVE_RD_INTX … #define DW_IC_TX_ABRT_7B_ADDR_NOACK … #define DW_IC_TX_ABRT_10ADDR1_NOACK … #define DW_IC_TX_ABRT_10ADDR2_NOACK … #define DW_IC_TX_ABRT_TXDATA_NOACK … #define DW_IC_TX_ABRT_GCALL_NOACK … #define DW_IC_TX_ABRT_GCALL_READ … #define DW_IC_TX_ABRT_SBYTE_ACKDET … #define DW_IC_TX_ABRT_SBYTE_NORSTRT … #define DW_IC_TX_ABRT_10B_RD_NORSTRT … #define DW_IC_TX_ABRT_MASTER_DIS … #define DW_IC_TX_ARB_LOST … #define DW_IC_RX_ABRT_SLAVE_RD_INTX … #define DW_IC_RX_ABRT_SLAVE_ARBLOST … #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO … #define DW_IC_TX_ABRT_NOACK … struct clk; struct device; struct reset_control; /** * struct dw_i2c_dev - private i2c-designware data * @dev: driver model device node * @map: IO registers map * @sysmap: System controller registers map * @base: IO registers pointer * @ext: Extended IO registers pointer * @cmd_complete: tx completion indicator * @clk: input reference clock * @pclk: clock required to access the registers * @rst: optional reset for the controller * @slave: represent an I2C slave device * @get_clk_rate_khz: callback to retrieve IP specific bus speed * @cmd_err: run time hadware error code * @msgs: points to an array of messages currently being transferred * @msgs_num: the number of elements in msgs * @msg_write_idx: the element index of the current tx message in the msgs array * @tx_buf_len: the length of the current tx buffer * @tx_buf: the current tx buffer * @msg_read_idx: the element index of the current rx message in the msgs array * @rx_buf_len: the length of the current rx buffer * @rx_buf: the current rx buffer * @msg_err: error status of the current transfer * @status: i2c master status, one of STATUS_* * @abort_source: copy of the TX_ABRT_SOURCE register * @sw_mask: SW mask of DW_IC_INTR_MASK used in polling mode * @irq: interrupt number for the i2c master * @flags: platform specific flags like type of IO accessors or model * @adapter: i2c subsystem adapter node * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support * @master_cfg: configuration for the master device * @slave_cfg: configuration for the slave device * @tx_fifo_depth: depth of the hardware tx fifo * @rx_fifo_depth: depth of the hardware rx fifo * @rx_outstanding: current master-rx elements in tx fifo * @timings: bus clock frequency, SDA hold and other timings * @sda_hold_time: SDA hold value * @ss_hcnt: standard speed HCNT value * @ss_lcnt: standard speed LCNT value * @fs_hcnt: fast speed HCNT value * @fs_lcnt: fast speed LCNT value * @fp_hcnt: fast plus HCNT value * @fp_lcnt: fast plus LCNT value * @hs_hcnt: high speed HCNT value * @hs_lcnt: high speed LCNT value * @acquire_lock: function to acquire a hardware lock on the bus * @release_lock: function to release a hardware lock on the bus * @semaphore_idx: Index of table with semaphore type attached to the bus. It's * -1 if there is no semaphore. * @shared_with_punit: true if this bus is shared with the SoCs PUNIT * @disable: function to disable the controller * @init: function to initialize the I2C hardware * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE * @rinfo: I²C GPIO recovery information * * HCNT and LCNT parameters can be used if the platform knows more accurate * values than the one computed based only on the input clock frequency. * Leave them to be %0 if not used. */ struct dw_i2c_dev { … }; #define ACCESS_INTR_MASK … #define ACCESS_NO_IRQ_SUSPEND … #define ARBITRATION_SEMAPHORE … #define ACCESS_POLLING … #define MODEL_MSCC_OCELOT … #define MODEL_BAIKAL_BT1 … #define MODEL_AMD_NAVI_GPU … #define MODEL_WANGXUN_SP … #define MODEL_MASK … /* * Enable UCSI interrupt by writing 0xd at register * offset 0x474 specified in hardware specification. */ #define AMD_UCSI_INTR_REG … #define AMD_UCSI_INTR_EN … #define TXGBE_TX_FIFO_DEPTH … #define TXGBE_RX_FIFO_DEPTH … struct i2c_dw_semaphore_callbacks { … }; int i2c_dw_init_regmap(struct dw_i2c_dev *dev); u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset); u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset); int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev); int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); void i2c_dw_release_lock(struct dw_i2c_dev *dev); int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev); u32 i2c_dw_func(struct i2c_adapter *adap); void i2c_dw_disable(struct dw_i2c_dev *dev); static inline void __i2c_dw_enable(struct dw_i2c_dev *dev) { … } static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev) { … } static inline void __i2c_dw_write_intr_mask(struct dw_i2c_dev *dev, unsigned int intr_mask) { … } static inline void __i2c_dw_read_intr_mask(struct dw_i2c_dev *dev, unsigned int *intr_mask) { … } void __i2c_dw_disable(struct dw_i2c_dev *dev); extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE) extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); #else static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; } #endif static inline int i2c_dw_probe(struct dw_i2c_dev *dev) { … } static inline void i2c_dw_configure(struct dw_i2c_dev *dev) { … } #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); #endif #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP) int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev); #endif int i2c_dw_validate_speed(struct dw_i2c_dev *dev); void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev); #if IS_ENABLED(CONFIG_ACPI) int i2c_dw_acpi_configure(struct device *device); #else static inline int i2c_dw_acpi_configure(struct device *device) { return -ENODEV; } #endif
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