// SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2014 Broadcom Corporation #include <linux/delay.h> #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #define IDM_CTRL_DIRECT_OFFSET … #define CFG_OFFSET … #define CFG_RESET_SHIFT … #define CFG_EN_SHIFT … #define CFG_SLAVE_ADDR_0_SHIFT … #define CFG_M_RETRY_CNT_SHIFT … #define CFG_M_RETRY_CNT_MASK … #define TIM_CFG_OFFSET … #define TIM_CFG_MODE_400_SHIFT … #define TIM_RAND_SLAVE_STRETCH_SHIFT … #define TIM_RAND_SLAVE_STRETCH_MASK … #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT … #define TIM_PERIODIC_SLAVE_STRETCH_MASK … #define S_CFG_SMBUS_ADDR_OFFSET … #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT … #define S_CFG_NIC_SMB_ADDR3_SHIFT … #define S_CFG_NIC_SMB_ADDR3_MASK … #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT … #define S_CFG_NIC_SMB_ADDR2_SHIFT … #define S_CFG_NIC_SMB_ADDR2_MASK … #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT … #define S_CFG_NIC_SMB_ADDR1_SHIFT … #define S_CFG_NIC_SMB_ADDR1_MASK … #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT … #define S_CFG_NIC_SMB_ADDR0_SHIFT … #define S_CFG_NIC_SMB_ADDR0_MASK … #define M_FIFO_CTRL_OFFSET … #define M_FIFO_RX_FLUSH_SHIFT … #define M_FIFO_TX_FLUSH_SHIFT … #define M_FIFO_RX_CNT_SHIFT … #define M_FIFO_RX_CNT_MASK … #define M_FIFO_RX_THLD_SHIFT … #define M_FIFO_RX_THLD_MASK … #define S_FIFO_CTRL_OFFSET … #define S_FIFO_RX_FLUSH_SHIFT … #define S_FIFO_TX_FLUSH_SHIFT … #define S_FIFO_RX_CNT_SHIFT … #define S_FIFO_RX_CNT_MASK … #define S_FIFO_RX_THLD_SHIFT … #define S_FIFO_RX_THLD_MASK … #define M_CMD_OFFSET … #define M_CMD_START_BUSY_SHIFT … #define M_CMD_STATUS_SHIFT … #define M_CMD_STATUS_MASK … #define M_CMD_STATUS_SUCCESS … #define M_CMD_STATUS_LOST_ARB … #define M_CMD_STATUS_NACK_ADDR … #define M_CMD_STATUS_NACK_DATA … #define M_CMD_STATUS_TIMEOUT … #define M_CMD_STATUS_FIFO_UNDERRUN … #define M_CMD_STATUS_RX_FIFO_FULL … #define M_CMD_PROTOCOL_SHIFT … #define M_CMD_PROTOCOL_MASK … #define M_CMD_PROTOCOL_QUICK … #define M_CMD_PROTOCOL_BLK_WR … #define M_CMD_PROTOCOL_BLK_RD … #define M_CMD_PROTOCOL_PROCESS … #define M_CMD_PEC_SHIFT … #define M_CMD_RD_CNT_SHIFT … #define M_CMD_RD_CNT_MASK … #define S_CMD_OFFSET … #define S_CMD_START_BUSY_SHIFT … #define S_CMD_STATUS_SHIFT … #define S_CMD_STATUS_MASK … #define S_CMD_STATUS_SUCCESS … #define S_CMD_STATUS_TIMEOUT … #define S_CMD_STATUS_MASTER_ABORT … #define IE_OFFSET … #define IE_M_RX_FIFO_FULL_SHIFT … #define IE_M_RX_THLD_SHIFT … #define IE_M_START_BUSY_SHIFT … #define IE_M_TX_UNDERRUN_SHIFT … #define IE_S_RX_FIFO_FULL_SHIFT … #define IE_S_RX_THLD_SHIFT … #define IE_S_RX_EVENT_SHIFT … #define IE_S_START_BUSY_SHIFT … #define IE_S_TX_UNDERRUN_SHIFT … #define IE_S_RD_EVENT_SHIFT … #define IS_OFFSET … #define IS_M_RX_FIFO_FULL_SHIFT … #define IS_M_RX_THLD_SHIFT … #define IS_M_START_BUSY_SHIFT … #define IS_M_TX_UNDERRUN_SHIFT … #define IS_S_RX_FIFO_FULL_SHIFT … #define IS_S_RX_THLD_SHIFT … #define IS_S_RX_EVENT_SHIFT … #define IS_S_START_BUSY_SHIFT … #define IS_S_TX_UNDERRUN_SHIFT … #define IS_S_RD_EVENT_SHIFT … #define M_TX_OFFSET … #define M_TX_WR_STATUS_SHIFT … #define M_TX_DATA_SHIFT … #define M_TX_DATA_MASK … #define M_RX_OFFSET … #define M_RX_STATUS_SHIFT … #define M_RX_STATUS_MASK … #define M_RX_PEC_ERR_SHIFT … #define M_RX_DATA_SHIFT … #define M_RX_DATA_MASK … #define S_TX_OFFSET … #define S_TX_WR_STATUS_SHIFT … #define S_TX_DATA_SHIFT … #define S_TX_DATA_MASK … #define S_RX_OFFSET … #define S_RX_STATUS_SHIFT … #define S_RX_STATUS_MASK … #define S_RX_PEC_ERR_SHIFT … #define S_RX_DATA_SHIFT … #define S_RX_DATA_MASK … #define I2C_TIMEOUT_MSEC … #define M_TX_RX_FIFO_SIZE … #define M_RX_FIFO_MAX_THLD_VALUE … #define M_RX_MAX_READ_LEN … #define M_RX_FIFO_THLD_VALUE … #define IE_M_ALL_INTERRUPT_SHIFT … #define IE_M_ALL_INTERRUPT_MASK … #define SLAVE_READ_WRITE_BIT_MASK … #define SLAVE_READ_WRITE_BIT_SHIFT … #define SLAVE_MAX_SIZE_TRANSACTION … #define SLAVE_CLOCK_STRETCH_TIME … #define IE_S_ALL_INTERRUPT_SHIFT … #define IE_S_ALL_INTERRUPT_MASK … /* * It takes ~18us to reading 10bytes of data, hence to keep tasklet * running for less time, max slave read per tasklet is set to 10 bytes. */ #define MAX_SLAVE_RX_PER_INT … enum i2c_slave_read_status { … }; enum bus_speed_index { … }; enum bcm_iproc_i2c_type { … }; struct bcm_iproc_i2c_dev { … }; /* tasklet to process slave rx data */ static void slave_rx_tasklet_fn(unsigned long); /* * Can be expanded in the future if more interrupt status bits are utilized */ #define ISR_MASK … #define ISR_MASK_SLAVE … static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave); static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave); static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, bool enable); static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, u32 offset) { … } static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, u32 offset, u32 val) { … } static void bcm_iproc_i2c_slave_init( struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) { … } static bool bcm_iproc_i2c_check_slave_status (struct bcm_iproc_i2c_dev *iproc_i2c, u32 status) { … } static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c) { … } static void slave_rx_tasklet_fn(unsigned long data) { … } static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, u32 status) { … } static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) { … } static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c) { … } static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c) { … } static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, u32 status) { … } static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) { … } static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) { … } static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, bool enable) { … } static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, struct i2c_msg *msg) { … } static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, struct i2c_msg *msg, u32 cmd) { … } /* * If 'process_call' is true, then this is a multi-msg transfer that requires * a repeated start between the messages. * More specifically, it must be a write (reg) followed by a read (data). * The i2c quirks are set to enforce this rule. */ static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c, struct i2c_msg *msgs, bool process_call) { … } static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg msgs[], int num) { … } static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) { … } static struct i2c_algorithm bcm_iproc_algo = …; static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = …; static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) { … } static int bcm_iproc_i2c_probe(struct platform_device *pdev) { … } static void bcm_iproc_i2c_remove(struct platform_device *pdev) { … } static int bcm_iproc_i2c_suspend(struct device *dev) { … } static int bcm_iproc_i2c_resume(struct device *dev) { … } static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = …; static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave) { … } static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) { … } static const struct of_device_id bcm_iproc_i2c_of_match[] = …; MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); static struct platform_driver bcm_iproc_i2c_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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