linux/drivers/i2c/busses/i2c-ocores.c

// SPDX-License-Identifier: GPL-2.0
/*
 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
 * (https://opencores.org/project/i2c/overview)
 *
 * Peter Korsgaard <[email protected]>
 *
 * Support for the GRLIB port of the controller by
 * Andreas Larsson <[email protected]>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/platform_data/i2c-ocores.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/log2.h>
#include <linux/spinlock.h>
#include <linux/jiffies.h>

/*
 * 'process_lock' exists because ocores_process() and ocores_process_timeout()
 * can't run in parallel.
 */
struct ocores_i2c {};

/* registers */
#define OCI2C_PRELOW
#define OCI2C_PREHIGH
#define OCI2C_CONTROL
#define OCI2C_DATA
#define OCI2C_CMD
#define OCI2C_STATUS

#define OCI2C_CTRL_IEN
#define OCI2C_CTRL_EN

#define OCI2C_CMD_START
#define OCI2C_CMD_STOP
#define OCI2C_CMD_READ
#define OCI2C_CMD_WRITE
#define OCI2C_CMD_READ_ACK
#define OCI2C_CMD_READ_NACK
#define OCI2C_CMD_IACK

#define OCI2C_STAT_IF
#define OCI2C_STAT_TIP
#define OCI2C_STAT_ARBLOST
#define OCI2C_STAT_BUSY
#define OCI2C_STAT_NACK

#define STATE_DONE
#define STATE_START
#define STATE_WRITE
#define STATE_READ
#define STATE_ERROR

#define TYPE_OCORES
#define TYPE_GRLIB

#define OCORES_FLAG_BROKEN_IRQ

static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
{}

static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
{}

static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
{}

static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
{}

static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
{}

static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
{}

static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
{}

static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
{}

static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
{}

static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
{}

static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
{}

static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
{}

static void ocores_process(struct ocores_i2c *i2c, u8 stat)
{}

static irqreturn_t ocores_isr(int irq, void *dev_id)
{}

/**
 * ocores_process_timeout() - Process timeout event
 * @i2c: ocores I2C device instance
 */
static void ocores_process_timeout(struct ocores_i2c *i2c)
{}

/**
 * ocores_wait() - Wait until something change in a given register
 * @i2c: ocores I2C device instance
 * @reg: register to query
 * @mask: bitmask to apply on register value
 * @val: expected result
 * @timeout: timeout in jiffies
 *
 * Timeout is necessary to avoid to stay here forever when the chip
 * does not answer correctly.
 *
 * Return: 0 on success, -ETIMEDOUT on timeout
 */
static int ocores_wait(struct ocores_i2c *i2c,
		       int reg, u8 mask, u8 val,
		       const unsigned long timeout)
{}

/**
 * ocores_poll_wait() - Wait until is possible to process some data
 * @i2c: ocores I2C device instance
 *
 * Used when the device is in polling mode (interrupts disabled).
 *
 * Return: 0 on success, -ETIMEDOUT on timeout
 */
static int ocores_poll_wait(struct ocores_i2c *i2c)
{}

/**
 * ocores_process_polling() - It handles an IRQ-less transfer
 * @i2c: ocores I2C device instance
 *
 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
 * (only that IRQ are not produced). This means that we can re-use entirely
 * ocores_isr(), we just add our polling code around it.
 *
 * It can run in atomic context
 *
 * Return: 0 on success, -ETIMEDOUT on timeout
 */
static int ocores_process_polling(struct ocores_i2c *i2c)
{}

static int ocores_xfer_core(struct ocores_i2c *i2c,
			    struct i2c_msg *msgs, int num,
			    bool polling)
{}

static int ocores_xfer_polling(struct i2c_adapter *adap,
			       struct i2c_msg *msgs, int num)
{}

static int ocores_xfer(struct i2c_adapter *adap,
		       struct i2c_msg *msgs, int num)
{}

static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
{}


static u32 ocores_func(struct i2c_adapter *adap)
{}

static struct i2c_algorithm ocores_algorithm =;

static const struct i2c_adapter ocores_adapter =;

static const struct of_device_id ocores_i2c_match[] =;
MODULE_DEVICE_TABLE(of, ocores_i2c_match);

#ifdef CONFIG_OF
/*
 * Read and write functions for the GRLIB port of the controller. Registers are
 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 * register. The subsequent registers have their offsets decreased accordingly.
 */
static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
{}

static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
{}

static int ocores_i2c_of_probe(struct platform_device *pdev,
				struct ocores_i2c *i2c)
{}
#else
#define ocores_i2c_of_probe
#endif

static int ocores_i2c_probe(struct platform_device *pdev)
{}

static void ocores_i2c_remove(struct platform_device *pdev)
{}

static int ocores_i2c_suspend(struct device *dev)
{}

static int ocores_i2c_resume(struct device *dev)
{}

static DEFINE_NOIRQ_DEV_PM_OPS(ocores_i2c_pm,
			       ocores_i2c_suspend, ocores_i2c_resume);

static struct platform_driver ocores_i2c_driver =;

module_platform_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();
MODULE_ALIAS();