/* SPDX-License-Identifier: GPL-2.0 */ #include <linux/atomic.h> #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/i2c.h> #include <linux/i2c-smbus.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/pci.h> /* Controller command patterns */ #define SW_TWSI_V … #define SW_TWSI_EIA … #define SW_TWSI_R … #define SW_TWSI_SOVR … #define SW_TWSI_SIZE_SHIFT … #define SW_TWSI_ADDR_SHIFT … #define SW_TWSI_IA_SHIFT … /* Controller opcode word (bits 60:57) */ #define SW_TWSI_OP_SHIFT … #define SW_TWSI_OP_7 … #define SW_TWSI_OP_7_IA … #define SW_TWSI_OP_10 … #define SW_TWSI_OP_10_IA … #define SW_TWSI_OP_TWSI_CLK … #define SW_TWSI_OP_EOP … /* Controller extended opcode word (bits 34:32) */ #define SW_TWSI_EOP_SHIFT … #define SW_TWSI_EOP_TWSI_DATA … #define SW_TWSI_EOP_TWSI_CTL … #define SW_TWSI_EOP_TWSI_CLKCTL … #define SW_TWSI_EOP_TWSI_STAT … #define SW_TWSI_EOP_TWSI_RST … /* Controller command and status bits */ #define TWSI_CTL_CE … #define TWSI_CTL_ENAB … #define TWSI_CTL_STA … #define TWSI_CTL_STP … #define TWSI_CTL_IFLG … #define TWSI_CTL_AAK … /* Status values */ #define STAT_BUS_ERROR … #define STAT_START … #define STAT_REP_START … #define STAT_TXADDR_ACK … #define STAT_TXADDR_NAK … #define STAT_TXDATA_ACK … #define STAT_TXDATA_NAK … #define STAT_LOST_ARB_38 … #define STAT_RXADDR_ACK … #define STAT_RXADDR_NAK … #define STAT_RXDATA_ACK … #define STAT_RXDATA_NAK … #define STAT_SLAVE_60 … #define STAT_LOST_ARB_68 … #define STAT_SLAVE_70 … #define STAT_LOST_ARB_78 … #define STAT_SLAVE_80 … #define STAT_SLAVE_88 … #define STAT_GENDATA_ACK … #define STAT_GENDATA_NAK … #define STAT_SLAVE_A0 … #define STAT_SLAVE_A8 … #define STAT_LOST_ARB_B0 … #define STAT_SLAVE_LOST … #define STAT_SLAVE_NAK … #define STAT_SLAVE_ACK … #define STAT_AD2W_ACK … #define STAT_AD2W_NAK … #define STAT_WDOG_TOUT … #define STAT_IDLE … /* TWSI_INT values */ #define TWSI_INT_ST_INT … #define TWSI_INT_TS_INT … #define TWSI_INT_CORE_INT … #define TWSI_INT_ST_EN … #define TWSI_INT_TS_EN … #define TWSI_INT_CORE_EN … #define TWSI_INT_SDA_OVR … #define TWSI_INT_SCL_OVR … #define TWSI_INT_SDA … #define TWSI_INT_SCL … #define I2C_OCTEON_EVENT_WAIT … /* Register offsets */ struct octeon_i2c_reg_offset { … }; #define OCTEON_REG_SW_TWSI(x) … #define OCTEON_REG_TWSI_INT(x) … #define OCTEON_REG_SW_TWSI_EXT(x) … #define OCTEON_REG_MODE(x) … /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ #define TWSX_MODE_REFCLK_SRC … #define TWSX_MODE_HS_MODE … #define TWSX_MODE_HS_MASK … /* Set BUS_MON_RST to reset bus monitor */ #define BUS_MON_RST_MASK … struct octeon_i2c { … }; static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr) { … } /** * octeon_i2c_reg_write - write an I2C core register * @i2c: The struct octeon_i2c * @eop_reg: Register selector * @data: Value to be written * * The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TWSI CSR. */ static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data) { … } #define octeon_i2c_ctl_write(i2c, val) … #define octeon_i2c_data_write(i2c, val) … /** * octeon_i2c_reg_read - read lower bits of an I2C core register * @i2c: The struct octeon_i2c * @eop_reg: Register selector * * Returns the data. * * The I2C core registers are accessed indirectly via the SW_TWSI CSR. */ static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg, int *error) { … } #define octeon_i2c_ctl_read(i2c) … #define octeon_i2c_data_read(i2c, error) … #define octeon_i2c_stat_read(i2c) … /** * octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register * @i2c: The struct octeon_i2c * * Returns the value of the register. */ static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c) { … } /** * octeon_i2c_write_int - write the OCTEON_REG_TWSI_INT register * @i2c: The struct octeon_i2c * @data: Value to be written */ static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) { … } #define IS_LS_FREQ(twsi_freq) … #define PCI_SUBSYS_DEVID_9XXX … #define PCI_SUBSYS_MASK … /** * octeon_i2c_is_otx2 - check for chip ID * @pdev: PCI dev structure * * Returns true if the device is an OcteonTX2, false otherwise. */ static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev) { … } /* Prototypes */ irqreturn_t octeon_i2c_isr(int irq, void *dev_id); int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c); void octeon_i2c_set_clock(struct octeon_i2c *i2c); extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;
Codebase Browser
linux