// SPDX-License-Identifier: GPL-2.0-only /* * i2c-xiic.c * Copyright (c) 2002-2007 Xilinx Inc. * Copyright (c) 2009-2010 Intel Corporation * * This code was implemented by Mocean Laboratories AB when porting linux * to the automotive development board Russellville. The copyright holder * as seen in the header is Intel corporation. * Mocean Laboratories forked off the GNU/Linux platform work into a * separate company called Pelagicore AB, which committed the code to the * kernel. */ /* Supports: * Xilinx IIC */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/errno.h> #include <linux/err.h> #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/completion.h> #include <linux/platform_data/i2c-xiic.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/of.h> #include <linux/clk.h> #include <linux/pm_runtime.h> #define DRIVER_NAME … #define DYNAMIC_MODE_READ_BROKEN_BIT … #define SMBUS_BLOCK_READ_MIN_LEN … enum xilinx_i2c_state { … }; enum xiic_endian { … }; enum i2c_scl_freq { … }; /** * struct xiic_i2c - Internal representation of the XIIC I2C bus * @dev: Pointer to device structure * @base: Memory base of the HW registers * @completion: Completion for callers * @adap: Kernel adapter representation * @tx_msg: Messages from above to be sent * @lock: Mutual exclusion * @tx_pos: Current pos in TX message * @nmsgs: Number of messages in tx_msg * @rx_msg: Current RX message * @rx_pos: Position within current RX message * @endianness: big/little-endian byte order * @clk: Pointer to AXI4-lite input clock * @state: See STATE_ * @singlemaster: Indicates bus is single master * @dynamic: Mode of controller * @prev_msg_tx: Previous message is Tx * @quirks: To hold platform specific bug info * @smbus_block_read: Flag to handle block read * @input_clk: Input clock to I2C controller * @i2c_clk: I2C SCL frequency */ struct xiic_i2c { … }; struct xiic_version_data { … }; /** * struct timing_regs - AXI I2C timing registers that depend on I2C spec * @tsusta: setup time for a repeated START condition * @tsusto: setup time for a STOP condition * @thdsta: hold time for a repeated START condition * @tsudat: setup time for data * @tbuf: bus free time between STOP and START */ struct timing_regs { … }; /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */ static const struct timing_regs timing_reg_values[] = …; #define XIIC_MSB_OFFSET … #define XIIC_REG_OFFSET … /* * Register offsets in bytes from RegisterBase. Three is added to the * base offset to access LSB (IBM style) of the word */ #define XIIC_CR_REG_OFFSET … #define XIIC_SR_REG_OFFSET … #define XIIC_DTR_REG_OFFSET … #define XIIC_DRR_REG_OFFSET … #define XIIC_ADR_REG_OFFSET … #define XIIC_TFO_REG_OFFSET … #define XIIC_RFO_REG_OFFSET … #define XIIC_TBA_REG_OFFSET … #define XIIC_RFD_REG_OFFSET … #define XIIC_GPO_REG_OFFSET … /* * Timing register offsets from RegisterBase. These are used only for * setting i2c clock frequency for the line. */ #define XIIC_TSUSTA_REG_OFFSET … #define XIIC_TSUSTO_REG_OFFSET … #define XIIC_THDSTA_REG_OFFSET … #define XIIC_TSUDAT_REG_OFFSET … #define XIIC_TBUF_REG_OFFSET … #define XIIC_THIGH_REG_OFFSET … #define XIIC_TLOW_REG_OFFSET … #define XIIC_THDDAT_REG_OFFSET … /* Control Register masks */ #define XIIC_CR_ENABLE_DEVICE_MASK … #define XIIC_CR_TX_FIFO_RESET_MASK … #define XIIC_CR_MSMS_MASK … #define XIIC_CR_DIR_IS_TX_MASK … #define XIIC_CR_NO_ACK_MASK … #define XIIC_CR_REPEATED_START_MASK … #define XIIC_CR_GENERAL_CALL_MASK … /* Status Register masks */ #define XIIC_SR_GEN_CALL_MASK … #define XIIC_SR_ADDR_AS_SLAVE_MASK … #define XIIC_SR_BUS_BUSY_MASK … #define XIIC_SR_MSTR_RDING_SLAVE_MASK … #define XIIC_SR_TX_FIFO_FULL_MASK … #define XIIC_SR_RX_FIFO_FULL_MASK … #define XIIC_SR_RX_FIFO_EMPTY_MASK … #define XIIC_SR_TX_FIFO_EMPTY_MASK … /* Interrupt Status Register masks Interrupt occurs when... */ #define XIIC_INTR_ARB_LOST_MASK … #define XIIC_INTR_TX_ERROR_MASK … #define XIIC_INTR_TX_EMPTY_MASK … #define XIIC_INTR_RX_FULL_MASK … #define XIIC_INTR_BNB_MASK … #define XIIC_INTR_AAS_MASK … #define XIIC_INTR_NAAS_MASK … #define XIIC_INTR_TX_HALF_MASK … /* The following constants specify the depth of the FIFOs */ #define IIC_RX_FIFO_DEPTH … #define IIC_TX_FIFO_DEPTH … /* The following constants specify groups of interrupts that are typically * enabled or disables at the same time */ #define XIIC_TX_INTERRUPTS … #define XIIC_TX_RX_INTERRUPTS … /* * Tx Fifo upper bit masks. */ #define XIIC_TX_DYN_START_MASK … #define XIIC_TX_DYN_STOP_MASK … /* Dynamic mode constants */ #define MAX_READ_LENGTH_DYNAMIC … /* * The following constants define the register offsets for the Interrupt * registers. There are some holes in the memory map for reserved addresses * to allow other registers to be added and still match the memory map of the * interrupt controller registers */ #define XIIC_DGIER_OFFSET … #define XIIC_IISR_OFFSET … #define XIIC_IIER_OFFSET … #define XIIC_RESETR_OFFSET … #define XIIC_RESET_MASK … #define XIIC_PM_TIMEOUT … /* timeout waiting for the controller to respond */ #define XIIC_I2C_TIMEOUT … /* timeout waiting for the controller finish transfers */ #define XIIC_XFER_TIMEOUT … /* * The following constant is used for the device global interrupt enable * register, to enable all interrupts for the device, this is the only bit * in the register */ #define XIIC_GINTR_ENABLE_MASK … #define xiic_tx_space(i2c) … #define xiic_rx_space(i2c) … static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); static void __xiic_start_xfer(struct xiic_i2c *i2c); /* * For the register read and write functions, a little-endian and big-endian * version are necessary. Endianness is detected during the probe function. * Only the least significant byte [doublet] of the register are ever * accessed. This requires an offset of 3 [2] from the base address for * big-endian systems. */ static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) { … } static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) { … } static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) { … } static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) { … } static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) { … } static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) { … } static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) { … } static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) { … } static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) { … } static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) { … } static int xiic_wait_tx_empty(struct xiic_i2c *i2c) { … } /** * xiic_setclk - Sets the configured clock rate * @i2c: Pointer to the xiic device structure * * The timing register values are calculated according to the input clock * frequency and configured scl frequency. For details, please refer the * AXI I2C PG and NXP I2C Spec. * Supported frequencies are 100KHz, 400KHz and 1MHz. * * Return: 0 on success (Supported frequency selected or not configurable in SW) * -EINVAL on failure (scl frequency not supported or THIGH is 0) */ static int xiic_setclk(struct xiic_i2c *i2c) { … } static int xiic_reinit(struct xiic_i2c *i2c) { … } static void xiic_deinit(struct xiic_i2c *i2c) { … } static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) { … } static void xiic_read_rx(struct xiic_i2c *i2c) { … } static int xiic_tx_fifo_space(struct xiic_i2c *i2c) { … } static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) { … } static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) { … } static irqreturn_t xiic_process(int irq, void *dev_id) { … } static int xiic_bus_busy(struct xiic_i2c *i2c) { … } static int xiic_busy(struct xiic_i2c *i2c) { … } static void xiic_start_recv(struct xiic_i2c *i2c) { … } static void xiic_start_send(struct xiic_i2c *i2c) { … } static void __xiic_start_xfer(struct xiic_i2c *i2c) { … } static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) { … } static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { … } static u32 xiic_func(struct i2c_adapter *adap) { … } static const struct i2c_algorithm xiic_algorithm = …; static const struct i2c_adapter xiic_adapter = …; #if defined(CONFIG_OF) static const struct xiic_version_data xiic_2_00 = …; static const struct of_device_id xiic_of_match[] = …; MODULE_DEVICE_TABLE(of, xiic_of_match); #endif static int xiic_i2c_probe(struct platform_device *pdev) { … } static void xiic_i2c_remove(struct platform_device *pdev) { … } static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) { … } static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops xiic_dev_pm_ops = …; static struct platform_driver xiic_i2c_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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