/* SPDX-License-Identifier: GPL-2.0-only */ /* * GOVR registers list for WM8505 chips * * Copyright (C) 2010 Ed Spiridonov <[email protected]> * Based on VIA/WonderMedia wm8510-govrh-reg.h * http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/ * drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h */ #ifndef _WM8505FB_REGS_H #define _WM8505FB_REGS_H /* * Color space select register, default value 0x1c * BIT0 GOVRH_DVO_YUV2RGB_ENABLE * BIT1 GOVRH_VGA_YUV2RGB_ENABLE * BIT2 GOVRH_RGB_MODE * BIT3 GOVRH_DAC_CLKINV * BIT4 GOVRH_BLANK_ZERO */ #define WMT_GOVR_COLORSPACE … /* * Another colorspace select register, default value 1 * BIT0 GOVRH_DVO_RGB * BIT1 GOVRH_DVO_YUV422 */ #define WMT_GOVR_COLORSPACE1 … #define WMT_GOVR_CONTRAST … #define WMT_GOVR_BRGHTNESS … /* Framubeffer address */ #define WMT_GOVR_FBADDR … #define WMT_GOVR_FBADDR1 … /* Offset of visible window */ #define WMT_GOVR_XPAN … #define WMT_GOVR_YPAN … #define WMT_GOVR_XRES … #define WMT_GOVR_XRES_VIRTUAL … #define WMT_GOVR_MIF_ENABLE … #define WMT_GOVR_FHI … #define WMT_GOVR_REG_UPDATE … /* * BIT0 GOVRH_DVO_OUTWIDTH * BIT1 GOVRH_DVO_SYNC_POLAR * BIT2 GOVRH_DVO_ENABLE */ #define WMT_GOVR_DVO_SET … /* Timing generator? */ #define WMT_GOVR_TG … /* Timings */ #define WMT_GOVR_TIMING_H_ALL … #define WMT_GOVR_TIMING_V_ALL … #define WMT_GOVR_TIMING_V_START … #define WMT_GOVR_TIMING_V_END … #define WMT_GOVR_TIMING_H_START … #define WMT_GOVR_TIMING_H_END … #define WMT_GOVR_TIMING_V_SYNC … #define WMT_GOVR_TIMING_H_SYNC … #endif /* _WM8505FB_REGS_H */
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