/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * V4L2 DV timings header. * * Copyright (C) 2012-2016 Hans Verkuil <[email protected]> */ #ifndef _V4L2_DV_TIMINGS_H #define _V4L2_DV_TIMINGS_H #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6)) /* Sadly gcc versions older than 4.6 have a bug in how they initialize anonymous unions where they require additional curly brackets. This violates the C1x standard. This workaround adds the curly brackets if needed. */ #define V4L2_INIT_BT_TIMINGS(_width, args...) … #else #define V4L2_INIT_BT_TIMINGS … #endif /* CEA-861-F timings (i.e. standard HDTV timings) */ #define V4L2_DV_BT_CEA_640X480P59_94 … /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X480I59_94 … #define V4L2_DV_BT_CEA_720X480P59_94 … /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X576I50 … #define V4L2_DV_BT_CEA_720X576P50 … #define V4L2_DV_BT_CEA_1280X720P24 … #define V4L2_DV_BT_CEA_1280X720P25 … #define V4L2_DV_BT_CEA_1280X720P30 … #define V4L2_DV_BT_CEA_1280X720P50 … #define V4L2_DV_BT_CEA_1280X720P60 … #define V4L2_DV_BT_CEA_1920X1080P24 … #define V4L2_DV_BT_CEA_1920X1080P25 … #define V4L2_DV_BT_CEA_1920X1080P30 … #define V4L2_DV_BT_CEA_1920X1080I50 … #define V4L2_DV_BT_CEA_1920X1080P50 … #define V4L2_DV_BT_CEA_1920X1080I60 … #define V4L2_DV_BT_CEA_1920X1080P60 … #define V4L2_DV_BT_CEA_3840X2160P24 … #define V4L2_DV_BT_CEA_3840X2160P25 … #define V4L2_DV_BT_CEA_3840X2160P30 … #define V4L2_DV_BT_CEA_3840X2160P50 … #define V4L2_DV_BT_CEA_3840X2160P60 … #define V4L2_DV_BT_CEA_4096X2160P24 … #define V4L2_DV_BT_CEA_4096X2160P25 … #define V4L2_DV_BT_CEA_4096X2160P30 … #define V4L2_DV_BT_CEA_4096X2160P50 … #define V4L2_DV_BT_CEA_4096X2160P60 … /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ #define V4L2_DV_BT_DMT_640X350P85 … #define V4L2_DV_BT_DMT_640X400P85 … #define V4L2_DV_BT_DMT_720X400P85 … /* VGA resolutions */ #define V4L2_DV_BT_DMT_640X480P60 … #define V4L2_DV_BT_DMT_640X480P72 … #define V4L2_DV_BT_DMT_640X480P75 … #define V4L2_DV_BT_DMT_640X480P85 … /* SVGA resolutions */ #define V4L2_DV_BT_DMT_800X600P56 … #define V4L2_DV_BT_DMT_800X600P60 … #define V4L2_DV_BT_DMT_800X600P72 … #define V4L2_DV_BT_DMT_800X600P75 … #define V4L2_DV_BT_DMT_800X600P85 … #define V4L2_DV_BT_DMT_800X600P120_RB … #define V4L2_DV_BT_DMT_848X480P60 … #define V4L2_DV_BT_DMT_1024X768I43 … /* XGA resolutions */ #define V4L2_DV_BT_DMT_1024X768P60 … #define V4L2_DV_BT_DMT_1024X768P70 … #define V4L2_DV_BT_DMT_1024X768P75 … #define V4L2_DV_BT_DMT_1024X768P85 … #define V4L2_DV_BT_DMT_1024X768P120_RB … /* XGA+ resolution */ #define V4L2_DV_BT_DMT_1152X864P75 … #define V4L2_DV_BT_DMT_1280X720P60 … /* WXGA resolutions */ #define V4L2_DV_BT_DMT_1280X768P60_RB … #define V4L2_DV_BT_DMT_1280X768P60 … #define V4L2_DV_BT_DMT_1280X768P75 … #define V4L2_DV_BT_DMT_1280X768P85 … #define V4L2_DV_BT_DMT_1280X768P120_RB … #define V4L2_DV_BT_DMT_1280X800P60_RB … #define V4L2_DV_BT_DMT_1280X800P60 … #define V4L2_DV_BT_DMT_1280X800P75 … #define V4L2_DV_BT_DMT_1280X800P85 … #define V4L2_DV_BT_DMT_1280X800P120_RB … #define V4L2_DV_BT_DMT_1280X960P60 … #define V4L2_DV_BT_DMT_1280X960P85 … #define V4L2_DV_BT_DMT_1280X960P120_RB … /* SXGA resolutions */ #define V4L2_DV_BT_DMT_1280X1024P60 … #define V4L2_DV_BT_DMT_1280X1024P75 … #define V4L2_DV_BT_DMT_1280X1024P85 … #define V4L2_DV_BT_DMT_1280X1024P120_RB … #define V4L2_DV_BT_DMT_1360X768P60 … #define V4L2_DV_BT_DMT_1360X768P120_RB … #define V4L2_DV_BT_DMT_1366X768P60 … #define V4L2_DV_BT_DMT_1366X768P60_RB … /* SXGA+ resolutions */ #define V4L2_DV_BT_DMT_1400X1050P60_RB … #define V4L2_DV_BT_DMT_1400X1050P60 … #define V4L2_DV_BT_DMT_1400X1050P75 … #define V4L2_DV_BT_DMT_1400X1050P85 … #define V4L2_DV_BT_DMT_1400X1050P120_RB … /* WXGA+ resolutions */ #define V4L2_DV_BT_DMT_1440X900P60_RB … #define V4L2_DV_BT_DMT_1440X900P60 … #define V4L2_DV_BT_DMT_1440X900P75 … #define V4L2_DV_BT_DMT_1440X900P85 … #define V4L2_DV_BT_DMT_1440X900P120_RB … #define V4L2_DV_BT_DMT_1600X900P60_RB … /* UXGA resolutions */ #define V4L2_DV_BT_DMT_1600X1200P60 … #define V4L2_DV_BT_DMT_1600X1200P65 … #define V4L2_DV_BT_DMT_1600X1200P70 … #define V4L2_DV_BT_DMT_1600X1200P75 … #define V4L2_DV_BT_DMT_1600X1200P85 … #define V4L2_DV_BT_DMT_1600X1200P120_RB … /* WSXGA+ resolutions */ #define V4L2_DV_BT_DMT_1680X1050P60_RB … #define V4L2_DV_BT_DMT_1680X1050P60 … #define V4L2_DV_BT_DMT_1680X1050P75 … #define V4L2_DV_BT_DMT_1680X1050P85 … #define V4L2_DV_BT_DMT_1680X1050P120_RB … #define V4L2_DV_BT_DMT_1792X1344P60 … #define V4L2_DV_BT_DMT_1792X1344P75 … #define V4L2_DV_BT_DMT_1792X1344P120_RB … #define V4L2_DV_BT_DMT_1856X1392P60 … #define V4L2_DV_BT_DMT_1856X1392P75 … #define V4L2_DV_BT_DMT_1856X1392P120_RB … #define V4L2_DV_BT_DMT_1920X1080P60 … /* WUXGA resolutions */ #define V4L2_DV_BT_DMT_1920X1200P60_RB … #define V4L2_DV_BT_DMT_1920X1200P60 … #define V4L2_DV_BT_DMT_1920X1200P75 … #define V4L2_DV_BT_DMT_1920X1200P85 … #define V4L2_DV_BT_DMT_1920X1200P120_RB … #define V4L2_DV_BT_DMT_1920X1440P60 … #define V4L2_DV_BT_DMT_1920X1440P75 … #define V4L2_DV_BT_DMT_1920X1440P120_RB … #define V4L2_DV_BT_DMT_2048X1152P60_RB … /* WQXGA resolutions */ #define V4L2_DV_BT_DMT_2560X1600P60_RB … #define V4L2_DV_BT_DMT_2560X1600P60 … #define V4L2_DV_BT_DMT_2560X1600P75 … #define V4L2_DV_BT_DMT_2560X1600P85 … #define V4L2_DV_BT_DMT_2560X1600P120_RB … /* 4K resolutions */ #define V4L2_DV_BT_DMT_4096X2160P60_RB … #define V4L2_DV_BT_DMT_4096X2160P59_94_RB … /* SDI timings definitions */ /* SMPTE-125M */ #define V4L2_DV_BT_SDI_720X487I60 … #endif
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