// SPDX-License-Identifier: GPL-2.0-only /* * Frame buffer device for IBM GXT4500P/6500P and GXT4000P/6000P * display adaptors * * Copyright (C) 2006 Paul Mackerras, IBM Corp. <[email protected]> */ #include <linux/aperture.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/fb.h> #include <linux/console.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/delay.h> #include <linux/string.h> #define PCI_DEVICE_ID_IBM_GXT4500P … #define PCI_DEVICE_ID_IBM_GXT6500P … #define PCI_DEVICE_ID_IBM_GXT4000P … #define PCI_DEVICE_ID_IBM_GXT6000P … /* GXT4500P registers */ /* Registers in PCI config space */ #define CFG_ENDIAN0 … /* Misc control/status registers */ #define STATUS … #define CTRL_REG0 … #define CR0_HALT_DMA … #define CR0_RASTER_RESET … #define CR0_GEOM_RESET … #define CR0_MEM_CTRLER_RESET … /* Framebuffer control registers */ #define FB_AB_CTRL … #define FB_CD_CTRL … #define FB_WID_CTRL … #define FB_Z_CTRL … #define FB_VGA_CTRL … #define REFRESH_AB_CTRL … #define REFRESH_CD_CTRL … #define FB_OVL_CTRL … #define FB_CTRL_TYPE … #define FB_CTRL_WIDTH_MASK … #define FB_CTRL_WIDTH_SHIFT … #define FB_CTRL_START_SEG_MASK … #define REFRESH_START … #define REFRESH_SIZE … /* "Direct" framebuffer access registers */ #define DFA_FB_A … #define DFA_FB_B … #define DFA_FB_C … #define DFA_FB_D … #define DFA_FB_ENABLE … #define DFA_FB_BASE_MASK … #define DFA_FB_STRIDE_1k … #define DFA_FB_STRIDE_2k … #define DFA_FB_STRIDE_4k … #define DFA_PIX_8BIT … #define DFA_PIX_16BIT_565 … #define DFA_PIX_16BIT_1555 … #define DFA_PIX_24BIT … #define DFA_PIX_32BIT … /* maps DFA_PIX_* to pixel size in bytes */ static const unsigned char pixsize[] = …; /* Display timing generator registers */ #define DTG_CONTROL … #define DTG_CTL_SCREEN_REFRESH … #define DTG_CTL_ENABLE … #define DTG_HORIZ_EXTENT … #define DTG_HORIZ_DISPLAY … #define DTG_HSYNC_START … #define DTG_HSYNC_END … #define DTG_HSYNC_END_COMP … #define DTG_VERT_EXTENT … #define DTG_VERT_DISPLAY … #define DTG_VSYNC_START … #define DTG_VSYNC_END … #define DTG_VERT_SHORT … /* PLL/RAMDAC registers */ #define DISP_CTL … #define DISP_CTL_OFF … #define SYNC_CTL … #define SYNC_CTL_SYNC_ON_RGB … #define SYNC_CTL_SYNC_OFF … #define SYNC_CTL_HSYNC_INV … #define SYNC_CTL_VSYNC_INV … #define SYNC_CTL_HSYNC_OFF … #define SYNC_CTL_VSYNC_OFF … #define PLL_M … #define PLL_N … #define PLL_POSTDIV … #define PLL_C … /* Hardware cursor */ #define CURSOR_X … #define CURSOR_Y … #define CURSOR_HOTSPOT … #define CURSOR_MODE … #define CURSOR_MODE_OFF … #define CURSOR_MODE_4BPP … #define CURSOR_PIXMAP … #define CURSOR_CMAP … /* Window attribute table */ #define WAT_FMT … #define WAT_FMT_24BIT … #define WAT_FMT_16BIT_565 … #define WAT_FMT_16BIT_1555 … #define WAT_FMT_32BIT … #define WAT_FMT_8BIT_332 … #define WAT_FMT_8BIT … #define WAT_FMT_NO_CMAP … #define WAT_CMAP_OFFSET … #define WAT_CTRL … #define WAT_CTRL_SEL_B … #define WAT_CTRL_NO_INC … #define WAT_GAMMA_CTRL … #define WAT_GAMMA_DISABLE … #define WAT_OVL_CTRL … /* Indexed by DFA_PIX_* values */ static const unsigned char watfmt[] = …; /* Colormap array; 1k entries of 4 bytes each */ #define CMAP … #define readreg(par, reg) … #define writereg(par, reg, val) … struct gxt4500_par { … }; /* mode requested by user */ static char *mode_option; /* default mode: 1280x1024 @ 60 Hz, 8 bpp */ static const struct fb_videomode defaultmode = …; /* List of supported cards */ enum gxt_cards { … }; /* Card-specific information */ static const struct cardinfo { … } cardinfo[] = …; /* * The refclk and VCO dividers appear to use a linear feedback shift * register, which gets reloaded when it reaches a terminal value, at * which point the divider output is toggled. Thus one can obtain * whatever divisor is required by putting the appropriate value into * the reload register. For a divisor of N, one puts the value from * the LFSR sequence that comes N-1 places before the terminal value * into the reload register. */ static const unsigned char mdivtab[] = …; static const unsigned char ndivtab[] = …; static int calc_pll(int period_ps, struct gxt4500_par *par) { … } static int calc_pixclock(struct gxt4500_par *par) { … } static int gxt4500_var_to_par(struct fb_var_screeninfo *var, struct gxt4500_par *par) { … } static const struct fb_bitfield eightbits = …; static const struct fb_bitfield nobits = …; static void gxt4500_unpack_pixfmt(struct fb_var_screeninfo *var, int pixfmt) { … } static int gxt4500_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { … } static int gxt4500_set_par(struct fb_info *info) { … } static int gxt4500_setcolreg(unsigned int reg, unsigned int red, unsigned int green, unsigned int blue, unsigned int transp, struct fb_info *info) { … } static int gxt4500_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) { … } static int gxt4500_blank(int blank, struct fb_info *info) { … } static const struct fb_fix_screeninfo gxt4500_fix = …; static const struct fb_ops gxt4500_ops = …; /* PCI functions */ static int gxt4500_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static void gxt4500_remove(struct pci_dev *pdev) { … } /* supported chipsets */ static const struct pci_device_id gxt4500_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl); static struct pci_driver gxt4500_driver = …; static int gxt4500_init(void) { … } module_init(…) …; static void __exit gxt4500_exit(void) { … } module_exit(gxt4500_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; module_param(mode_option, charp, 0); MODULE_PARM_DESC(…) …;
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