// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2017 Intel Corporation. #include <linux/acpi.h> #include <linux/i2c.h> #include <linux/module.h> #include <linux/pm_runtime.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-event.h> #include <media/v4l2-fwnode.h> #define OV13858_REG_VALUE_08BIT … #define OV13858_REG_VALUE_16BIT … #define OV13858_REG_VALUE_24BIT … #define OV13858_REG_MODE_SELECT … #define OV13858_MODE_STANDBY … #define OV13858_MODE_STREAMING … #define OV13858_REG_SOFTWARE_RST … #define OV13858_SOFTWARE_RST … /* PLL1 generates PCLK and MIPI_PHY_CLK */ #define OV13858_REG_PLL1_CTRL_0 … #define OV13858_REG_PLL1_CTRL_1 … #define OV13858_REG_PLL1_CTRL_2 … #define OV13858_REG_PLL1_CTRL_3 … #define OV13858_REG_PLL1_CTRL_4 … #define OV13858_REG_PLL1_CTRL_5 … /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */ #define OV13858_REG_PLL2_CTRL_B … #define OV13858_REG_PLL2_CTRL_C … #define OV13858_REG_PLL2_CTRL_D … #define OV13858_REG_PLL2_CTRL_E … #define OV13858_REG_PLL2_CTRL_F … #define OV13858_REG_PLL2_CTRL_12 … #define OV13858_REG_MIPI_SC_CTRL0 … #define OV13858_REG_MIPI_SC_CTRL1 … /* Chip ID */ #define OV13858_REG_CHIP_ID … #define OV13858_CHIP_ID … /* V_TIMING internal */ #define OV13858_REG_VTS … #define OV13858_VTS_30FPS … #define OV13858_VTS_60FPS … #define OV13858_VTS_MAX … /* HBLANK control - read only */ #define OV13858_PPL_270MHZ … #define OV13858_PPL_540MHZ … /* Exposure control */ #define OV13858_REG_EXPOSURE … #define OV13858_EXPOSURE_MIN … #define OV13858_EXPOSURE_STEP … #define OV13858_EXPOSURE_DEFAULT … /* Analog gain control */ #define OV13858_REG_ANALOG_GAIN … #define OV13858_ANA_GAIN_MIN … #define OV13858_ANA_GAIN_MAX … #define OV13858_ANA_GAIN_STEP … #define OV13858_ANA_GAIN_DEFAULT … /* Digital gain control */ #define OV13858_REG_B_MWB_GAIN … #define OV13858_REG_G_MWB_GAIN … #define OV13858_REG_R_MWB_GAIN … #define OV13858_DGTL_GAIN_MIN … #define OV13858_DGTL_GAIN_MAX … #define OV13858_DGTL_GAIN_DEFAULT … #define OV13858_DGTL_GAIN_STEP … /* Test Pattern Control */ #define OV13858_REG_TEST_PATTERN … #define OV13858_TEST_PATTERN_ENABLE … #define OV13858_TEST_PATTERN_MASK … /* Number of frames to skip */ #define OV13858_NUM_OF_SKIP_FRAMES … struct ov13858_reg { … }; struct ov13858_reg_list { … }; /* Link frequency config */ struct ov13858_link_freq_config { … }; /* Mode : resolution and related config&values */ struct ov13858_mode { … }; /* 4224x3136 needs 1080Mbps/lane, 4 lanes */ static const struct ov13858_reg mipi_data_rate_1080mbps[] = …; /* * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane, * 4 lanes */ static const struct ov13858_reg mipi_data_rate_540mbps[] = …; static const struct ov13858_reg mode_4224x3136_regs[] = …; static const struct ov13858_reg mode_2112x1568_regs[] = …; static const struct ov13858_reg mode_2112x1188_regs[] = …; static const struct ov13858_reg mode_1056x784_regs[] = …; static const char * const ov13858_test_pattern_menu[] = …; /* Configurations for supported link frequencies */ #define OV13858_NUM_OF_LINK_FREQS … #define OV13858_LINK_FREQ_540MHZ … #define OV13858_LINK_FREQ_270MHZ … #define OV13858_LINK_FREQ_INDEX_0 … #define OV13858_LINK_FREQ_INDEX_1 … /* * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample * data rate => double data rate; number of lanes => 4; bits per pixel => 10 */ static u64 link_freq_to_pixel_rate(u64 f) { … } /* Menu items for LINK_FREQ V4L2 control */ static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = …; /* Link frequency configs */ static const struct ov13858_link_freq_config link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = …; /* Mode configs */ static const struct ov13858_mode supported_modes[] = …; struct ov13858 { … }; #define to_ov13858(_sd) … /* Read registers up to 4 at a time */ static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 *val) { … } /* Write registers up to 4 at a time */ static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 __val) { … } /* Write a list of registers */ static int ov13858_write_regs(struct ov13858 *ov13858, const struct ov13858_reg *regs, u32 len) { … } static int ov13858_write_reg_list(struct ov13858 *ov13858, const struct ov13858_reg_list *r_list) { … } /* Open sub-device */ static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { … } static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain) { … } static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern) { … } static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl) { … } static const struct v4l2_ctrl_ops ov13858_ctrl_ops = …; static int ov13858_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { … } static int ov13858_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { … } static void ov13858_update_pad_format(const struct ov13858_mode *mode, struct v4l2_subdev_format *fmt) { … } static int ov13858_do_get_pad_format(struct ov13858 *ov13858, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int ov13858_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int ov13858_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) { … } /* Start streaming */ static int ov13858_start_streaming(struct ov13858 *ov13858) { … } /* Stop streaming */ static int ov13858_stop_streaming(struct ov13858 *ov13858) { … } static int ov13858_set_stream(struct v4l2_subdev *sd, int enable) { … } /* Verify chip ID */ static int ov13858_identify_module(struct ov13858 *ov13858) { … } static const struct v4l2_subdev_core_ops ov13858_core_ops = …; static const struct v4l2_subdev_video_ops ov13858_video_ops = …; static const struct v4l2_subdev_pad_ops ov13858_pad_ops = …; static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = …; static const struct v4l2_subdev_ops ov13858_subdev_ops = …; static const struct media_entity_operations ov13858_subdev_entity_ops = …; static const struct v4l2_subdev_internal_ops ov13858_internal_ops = …; /* Initialize control handlers */ static int ov13858_init_controls(struct ov13858 *ov13858) { … } static void ov13858_free_controls(struct ov13858 *ov13858) { … } static int ov13858_probe(struct i2c_client *client) { … } static void ov13858_remove(struct i2c_client *client) { … } static const struct i2c_device_id ov13858_id_table[] = …; MODULE_DEVICE_TABLE(i2c, ov13858_id_table); #ifdef CONFIG_ACPI static const struct acpi_device_id ov13858_acpi_ids[] = …; MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids); #endif static struct i2c_driver ov13858_i2c_driver = …; module_i2c_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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