// SPDX-License-Identifier: GPL-2.0-only /* * ov2640 Camera Driver * * Copyright (C) 2010 Alberto Panizzo <[email protected]> * * Based on ov772x, ov9640 drivers and previous non merged implementations. * * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2006, OmniVision */ #include <linux/init.h> #include <linux/module.h> #include <linux/i2c.h> #include <linux/clk.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/v4l2-mediabus.h> #include <linux/videodev2.h> #include <media/v4l2-device.h> #include <media/v4l2-event.h> #include <media/v4l2-subdev.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-image-sizes.h> #define VAL_SET(x, mask, rshift, lshift) … /* * DSP registers * register offset for BANK_SEL == BANK_SEL_DSP */ #define R_BYPASS … #define R_BYPASS_DSP_BYPAS … #define R_BYPASS_USE_DSP … #define QS … #define CTRLI … #define CTRLI_LP_DP … #define CTRLI_ROUND … #define CTRLI_V_DIV_SET(x) … #define CTRLI_H_DIV_SET(x) … #define HSIZE … #define HSIZE_SET(x) … #define VSIZE … #define VSIZE_SET(x) … #define XOFFL … #define XOFFL_SET(x) … #define YOFFL … #define YOFFL_SET(x) … #define VHYX … #define VHYX_VSIZE_SET(x) … #define VHYX_HSIZE_SET(x) … #define VHYX_YOFF_SET(x) … #define VHYX_XOFF_SET(x) … #define DPRP … #define TEST … #define TEST_HSIZE_SET(x) … #define ZMOW … #define ZMOW_OUTW_SET(x) … #define ZMOH … #define ZMOH_OUTH_SET(x) … #define ZMHH … #define ZMHH_ZSPEED_SET(x) … #define ZMHH_OUTH_SET(x) … #define ZMHH_OUTW_SET(x) … #define BPADDR … #define BPDATA … #define CTRL2 … #define CTRL2_DCW_EN … #define CTRL2_SDE_EN … #define CTRL2_UV_ADJ_EN … #define CTRL2_UV_AVG_EN … #define CTRL2_CMX_EN … #define CTRL3 … #define CTRL3_BPC_EN … #define CTRL3_WPC_EN … #define SIZEL … #define SIZEL_HSIZE8_11_SET(x) … #define SIZEL_HSIZE8_SET(x) … #define SIZEL_VSIZE8_SET(x) … #define HSIZE8 … #define HSIZE8_SET(x) … #define VSIZE8 … #define VSIZE8_SET(x) … #define CTRL0 … #define CTRL0_AEC_EN … #define CTRL0_AEC_SEL … #define CTRL0_STAT_SEL … #define CTRL0_VFIRST … #define CTRL0_YUV422 … #define CTRL0_YUV_EN … #define CTRL0_RGB_EN … #define CTRL0_RAW_EN … #define CTRL1 … #define CTRL1_CIP … #define CTRL1_DMY … #define CTRL1_RAW_GMA … #define CTRL1_DG … #define CTRL1_AWB … #define CTRL1_AWB_GAIN … #define CTRL1_LENC … #define CTRL1_PRE … /* REG 0xC7 (unknown name): affects Auto White Balance (AWB) * AWB_OFF 0x40 * AWB_SIMPLE 0x10 * AWB_ON 0x00 (Advanced AWB ?) */ #define R_DVP_SP … #define R_DVP_SP_AUTO_MODE … #define R_DVP_SP_DVP_MASK … #define IMAGE_MODE … #define IMAGE_MODE_Y8_DVP_EN … #define IMAGE_MODE_JPEG_EN … #define IMAGE_MODE_YUV422 … #define IMAGE_MODE_RAW10 … #define IMAGE_MODE_RGB565 … #define IMAGE_MODE_HREF_VSYNC … #define IMAGE_MODE_LBYTE_FIRST … #define RESET … #define RESET_MICROC … #define RESET_SCCB … #define RESET_JPEG … #define RESET_DVP … #define RESET_IPU … #define RESET_CIF … #define REGED … #define REGED_CLK_OUT_DIS … #define MS_SP … #define SS_ID … #define SS_CTRL … #define SS_CTRL_ADD_AUTO_INC … #define SS_CTRL_EN … #define SS_CTRL_DELAY_CLK … #define SS_CTRL_ACC_EN … #define SS_CTRL_SEN_PASS_THR … #define MC_BIST … #define MC_BIST_RESET … #define MC_BIST_BOOT_ROM_SEL … #define MC_BIST_12KB_SEL … #define MC_BIST_12KB_MASK … #define MC_BIST_512KB_SEL … #define MC_BIST_512KB_MASK … #define MC_BIST_BUSY_BIT_R … #define MC_BIST_MC_RES_ONE_SH_W … #define MC_BIST_LAUNCH … #define BANK_SEL … #define BANK_SEL_DSP … #define BANK_SEL_SENS … /* * Sensor registers * register offset for BANK_SEL == BANK_SEL_SENS */ #define GAIN … #define COM1 … #define COM1_1_DUMMY_FR … #define COM1_3_DUMMY_FR … #define COM1_7_DUMMY_FR … #define COM1_VWIN_LSB_UXGA … #define COM1_VWIN_LSB_SVGA … #define COM1_VWIN_LSB_CIF … #define REG04 … #define REG04_DEF … #define REG04_HFLIP_IMG … #define REG04_VFLIP_IMG … #define REG04_VREF_EN … #define REG04_HREF_EN … #define REG04_AEC_SET(x) … #define REG08 … #define COM2 … #define COM2_SOFT_SLEEP_MODE … /* Output drive capability */ #define COM2_OCAP_Nx_SET(N) … #define PID … #define VER … #define COM3 … #define COM3_BAND_50H … #define COM3_BAND_AUTO … #define COM3_SING_FR_SNAPSH … #define AEC … #define CLKRC … #define CLKRC_EN … #define CLKRC_DIV_SET(x) … #define COM7 … #define COM7_SRST … #define COM7_RES_UXGA … #define COM7_RES_SVGA … #define COM7_RES_CIF … #define COM7_ZOOM_EN … #define COM7_COLOR_BAR_TEST … #define COM8 … #define COM8_DEF … #define COM8_BNDF_EN … #define COM8_AGC_EN … #define COM8_AEC_EN … #define COM9 … #define COM9_AGC_GAIN_2x … #define COM9_AGC_GAIN_4x … #define COM9_AGC_GAIN_8x … #define COM9_AGC_GAIN_16x … #define COM9_AGC_GAIN_32x … #define COM9_AGC_GAIN_64x … #define COM9_AGC_GAIN_128x … #define COM10 … #define COM10_PCLK_HREF … #define COM10_PCLK_RISE … #define COM10_HREF_INV … #define COM10_VSINC_INV … #define HSTART … #define HEND … #define VSTART … #define VEND … #define MIDH … #define MIDL … #define AEW … #define AEB … #define VV … #define VV_HIGH_TH_SET(x) … #define VV_LOW_TH_SET(x) … #define REG2A … #define FRARL … #define ADDVFL … #define ADDVFH … #define YAVG … #define REG32 … #define REG32_PCLK_DIV_2 … #define REG32_PCLK_DIV_4 … #define ARCOM2 … #define REG45 … #define FLL … #define FLH … #define COM19 … #define ZOOMS … #define COM22 … #define COM25 … #define COM25_50HZ_BANDING_AEC_MSBS_MASK … #define COM25_60HZ_BANDING_AEC_MSBS_MASK … #define COM25_50HZ_BANDING_AEC_MSBS_SET(x) … #define COM25_60HZ_BANDING_AEC_MSBS_SET(x) … #define BD50 … #define BD50_50HZ_BANDING_AEC_LSBS_SET(x) … #define BD60 … #define BD60_60HZ_BANDING_AEC_LSBS_SET(x) … #define REG5A … #define BD50_MAX_AEC_STEP_MASK … #define BD60_MAX_AEC_STEP_MASK … #define BD50_MAX_AEC_STEP_SET(x) … #define BD60_MAX_AEC_STEP_SET(x) … #define REG5D … #define REG5E … #define REG5F … #define REG60 … #define HISTO_LOW … #define HISTO_HIGH … /* * ID */ #define MANUFACTURER_ID … #define PID_OV2640 … #define VERSION(pid, ver) … /* * Struct */ struct regval_list { … }; struct ov2640_win_size { … }; struct ov2640_priv { … }; /* * Registers settings */ #define ENDMARKER … static const struct regval_list ov2640_init_regs[] = …; /* * Register settings for window size * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. * Then the different zooming configurations will setup the output image size. */ static const struct regval_list ov2640_size_change_preamble_regs[] = …; #define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) … static const struct regval_list ov2640_qcif_regs[] = …; static const struct regval_list ov2640_qvga_regs[] = …; static const struct regval_list ov2640_cif_regs[] = …; static const struct regval_list ov2640_vga_regs[] = …; static const struct regval_list ov2640_svga_regs[] = …; static const struct regval_list ov2640_xga_regs[] = …; static const struct regval_list ov2640_sxga_regs[] = …; static const struct regval_list ov2640_uxga_regs[] = …; #define OV2640_SIZE(n, w, h, r) … static const struct ov2640_win_size ov2640_supported_win_sizes[] = …; /* * Register settings for pixel formats */ static const struct regval_list ov2640_format_change_preamble_regs[] = …; static const struct regval_list ov2640_yuyv_regs[] = …; static const struct regval_list ov2640_uyvy_regs[] = …; static const struct regval_list ov2640_rgb565_be_regs[] = …; static const struct regval_list ov2640_rgb565_le_regs[] = …; static u32 ov2640_codes[] = …; /* * General functions */ static struct ov2640_priv *to_ov2640(const struct i2c_client *client) { … } static int ov2640_write_array(struct i2c_client *client, const struct regval_list *vals) { … } static int ov2640_mask_set(struct i2c_client *client, u8 reg, u8 mask, u8 set) { … } static int ov2640_reset(struct i2c_client *client) { … } static const char * const ov2640_test_pattern_menu[] = …; /* * functions */ static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl) { … } #ifdef CONFIG_VIDEO_ADV_DEBUG static int ov2640_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) { … } static int ov2640_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) { … } #endif static void ov2640_set_power(struct ov2640_priv *priv, int on) { … } static int ov2640_s_power(struct v4l2_subdev *sd, int on) { … } /* Select the nearest higher resolution for capture */ static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height) { … } static int ov2640_set_params(struct i2c_client *client, const struct ov2640_win_size *win, u32 code) { … } static int ov2640_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *format) { … } static int ov2640_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *format) { … } static int ov2640_init_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state) { … } static int ov2640_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { … } static int ov2640_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_selection *sel) { … } static int ov2640_s_stream(struct v4l2_subdev *sd, int on) { … } static int ov2640_video_probe(struct i2c_client *client) { … } static const struct v4l2_ctrl_ops ov2640_ctrl_ops = …; static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = …; static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = …; static const struct v4l2_subdev_video_ops ov2640_subdev_video_ops = …; static const struct v4l2_subdev_ops ov2640_subdev_ops = …; static const struct v4l2_subdev_internal_ops ov2640_internal_ops = …; static int ov2640_probe_dt(struct i2c_client *client, struct ov2640_priv *priv) { … } /* * i2c_driver functions */ static int ov2640_probe(struct i2c_client *client) { … } static void ov2640_remove(struct i2c_client *client) { … } static const struct i2c_device_id ov2640_id[] = …; MODULE_DEVICE_TABLE(i2c, ov2640_id); static const struct of_device_id ov2640_of_match[] = …; MODULE_DEVICE_TABLE(of, ov2640_of_match); static struct i2c_driver ov2640_i2c_driver = …; module_i2c_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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