// SPDX-License-Identifier: GPL-2.0-only /* * Omnivision OV9650/OV9652 CMOS Image Sensor driver * * Copyright (C) 2013, Sylwester Nawrocki <[email protected]> * * Register definitions and initial settings based on a driver written * by Vladimir Fonov. * Copyright (c) 2010, Vladimir Fonov */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/kernel.h> #include <linux/media.h> #include <linux/module.h> #include <linux/ratelimit.h> #include <linux/regmap.h> #include <linux/slab.h> #include <linux/string.h> #include <linux/videodev2.h> #include <media/media-entity.h> #include <media/v4l2-async.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-event.h> #include <media/v4l2-image-sizes.h> #include <media/v4l2-subdev.h> #include <media/v4l2-mediabus.h> static int debug; module_param(debug, int, 0644); MODULE_PARM_DESC(…) …; #define DRIVER_NAME … /* * OV9650/OV9652 register definitions */ #define REG_GAIN … #define REG_BLUE … #define REG_RED … #define REG_VREF … #define VREF_GAIN_MASK … #define REG_COM1 … #define COM1_CCIR656 … #define REG_B_AVE … #define REG_GB_AVE … #define REG_GR_AVE … #define REG_R_AVE … #define REG_COM2 … #define REG_PID … #define REG_VER … #define REG_COM3 … #define COM3_SWAP … #define COM3_VARIOPIXEL1 … #define REG_COM4 … #define COM4_VARIOPIXEL2 … #define REG_COM5 … #define COM5_SLAVE_MODE … #define COM5_SYSTEMCLOCK48MHZ … #define REG_COM6 … #define REG_AECH … #define REG_CLKRC … #define CLK_EXT … #define CLK_SCALE … #define REG_COM7 … #define COM7_RESET … #define COM7_FMT_MASK … #define COM7_FMT_VGA … #define COM7_FMT_CIF … #define COM7_FMT_QVGA … #define COM7_FMT_QCIF … #define COM7_RGB … #define COM7_YUV … #define COM7_BAYER … #define COM7_PBAYER … #define REG_COM8 … #define COM8_FASTAEC … #define COM8_AECSTEP … #define COM8_BFILT … #define COM8_AGC … #define COM8_AWB … #define COM8_AEC … #define REG_COM9 … #define COM9_GAIN_CEIL_MASK … #define REG_COM10 … #define COM10_HSYNC … #define COM10_PCLK_HB … #define COM10_HREF_REV … #define COM10_VS_LEAD … #define COM10_VS_NEG … #define COM10_HS_NEG … #define REG_HSTART … #define REG_HSTOP … #define REG_VSTART … #define REG_VSTOP … #define REG_PSHFT … #define REG_MIDH … #define REG_MIDL … #define REG_MVFP … #define MVFP_MIRROR … #define MVFP_FLIP … #define REG_BOS … #define REG_GBOS … #define REG_GROS … #define REG_ROS … #define REG_AEW … #define REG_AEB … #define REG_VPT … #define REG_BBIAS … #define REG_GBBIAS … #define REG_GRCOM … #define REG_EXHCH … #define REG_EXHCL … #define REG_RBIAS … #define REG_ADVFL … #define REG_ADVFH … #define REG_YAVE … #define REG_HSYST … #define REG_HSYEN … #define REG_HREF … #define REG_CHLF … #define REG_ADC … #define REG_ACOM … #define REG_OFON … #define OFON_PWRDN … #define REG_TSLB … #define TSLB_YUYV_MASK … #define REG_COM11 … #define COM11_NIGHT … #define COM11_NMFR … #define COM11_BANDING … #define COM11_AEC_REF_MASK … #define REG_COM12 … #define COM12_HREF … #define REG_COM13 … #define COM13_GAMMA … #define COM13_UVSAT … #define COM13_UVSWAP … #define REG_COM14 … #define COM14_EDGE_EN … #define COM14_EEF_X2 … #define REG_EDGE … #define EDGE_FACTOR_MASK … #define REG_COM15 … #define COM15_R10F0 … #define COM15_R01FE … #define COM15_R00FF … #define COM15_RGB565 … #define COM15_RGB555 … #define COM15_SWAPRB … #define REG_COM16 … #define REG_COM17 … /* n = 1...9, 0x4f..0x57 */ #define REG_MTX(__n) … #define REG_MTXS … /* Lens Correction Option 1...5, __n = 0...5 */ #define REG_LCC(__n) … #define LCC5_LCC_ENABLE … #define LCC5_LCC_COLOR … #define REG_MANU … #define REG_MANV … #define REG_HV … #define REG_MBD … #define REG_DBLV … #define REG_GSP … #define GSP_LEN … #define REG_GST … #define GST_LEN … #define REG_COM21 … #define REG_COM22 … #define COM22_WHTPCOR … #define COM22_WHTPCOROPT … #define COM22_DENOISE … #define REG_COM23 … #define COM23_TEST_MODE … #define REG_DBLC1 … #define REG_DBLC_B … #define REG_DBLC_R … #define REG_DM_LNL … #define REG_DM_LNH … #define REG_LCCFB … #define REG_LCCFR … #define REG_DBLC_GB … #define REG_DBLC_GR … #define REG_AECHM … #define REG_BD50ST … #define REG_BD60ST … #define REG_NULL … #define DEF_CLKRC … #define OV965X_ID(_msb, _lsb) … #define OV9650_ID … #define OV9652_ID … struct ov965x_ctrls { … }; struct ov965x_framesize { … }; struct ov965x_interval { … }; enum gpio_id { … }; struct ov965x { … }; struct i2c_rv { … }; static const struct i2c_rv ov965x_init_regs[] = …; #define NUM_FMT_REGS … /* * COM7, COM3, COM4, HSTART, HSTOP, HREF, VSTART, VSTOP, VREF, * EXHCH, EXHCL, ADC, OCOM, OFON */ static const u8 frame_size_reg_addr[NUM_FMT_REGS] = …; static const u8 ov965x_sxga_regs[NUM_FMT_REGS] = …; static const u8 ov965x_vga_regs[NUM_FMT_REGS] = …; /* Determined empirically. */ static const u8 ov965x_qvga_regs[NUM_FMT_REGS] = …; static const struct ov965x_framesize ov965x_framesizes[] = …; struct ov965x_pixfmt { … }; static const struct ov965x_pixfmt ov965x_formats[] = …; /* * This table specifies possible frame resolution and interval * combinations. Default CLKRC[5:0] divider values are valid * only for 24 MHz external clock frequency. */ static struct ov965x_interval ov965x_intervals[] = …; static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) { … } static inline struct ov965x *to_ov965x(struct v4l2_subdev *sd) { … } static int ov965x_read(struct ov965x *ov965x, u8 addr, u8 *val) { … } static int ov965x_write(struct ov965x *ov965x, u8 addr, u8 val) { … } static int ov965x_write_array(struct ov965x *ov965x, const struct i2c_rv *regs) { … } static int ov965x_set_default_gamma_curve(struct ov965x *ov965x) { static const u8 gamma_curve[] = { /* Values taken from OV application note. */ 0x40, 0x30, 0x4b, 0x60, 0x70, 0x70, 0x70, 0x70, 0x60, 0x60, 0x50, 0x48, 0x3a, 0x2e, 0x28, 0x22, 0x04, 0x07, 0x10, 0x28, 0x36, 0x44, 0x52, 0x60, 0x6c, 0x78, 0x8c, 0x9e, 0xbb, 0xd2, 0xe6 }; u8 addr = REG_GSP; unsigned int i; for (i = 0; i < ARRAY_SIZE(gamma_curve); i++) { int ret = ov965x_write(ov965x, addr, gamma_curve[i]); if (ret < 0) return ret; addr++; } return 0; }; static int ov965x_set_color_matrix(struct ov965x *ov965x) { … } static int __ov965x_set_power(struct ov965x *ov965x, int on) { … } static int ov965x_s_power(struct v4l2_subdev *sd, int on) { … } /* * V4L2 controls */ static void ov965x_update_exposure_ctrl(struct ov965x *ov965x) { … } static int ov965x_set_banding_filter(struct ov965x *ov965x, int value) { … } static int ov965x_set_white_balance(struct ov965x *ov965x, int awb) { … } #define NUM_BR_LEVELS … #define NUM_BR_REGS … static int ov965x_set_brightness(struct ov965x *ov965x, int val) { … } static int ov965x_set_gain(struct ov965x *ov965x, int auto_gain) { … } static int ov965x_set_sharpness(struct ov965x *ov965x, unsigned int value) { … } static int ov965x_set_exposure(struct ov965x *ov965x, int exp) { … } static int ov965x_set_flip(struct ov965x *ov965x) { … } #define NUM_SAT_LEVELS … #define NUM_SAT_REGS … static int ov965x_set_saturation(struct ov965x *ov965x, int val) { … } static int ov965x_set_test_pattern(struct ov965x *ov965x, int value) { … } static int __g_volatile_ctrl(struct ov965x *ov965x, struct v4l2_ctrl *ctrl) { … } static int ov965x_g_volatile_ctrl(struct v4l2_ctrl *ctrl) { … } static int ov965x_s_ctrl(struct v4l2_ctrl *ctrl) { … } static const struct v4l2_ctrl_ops ov965x_ctrl_ops = …; static const char * const test_pattern_menu[] = …; static int ov965x_initialize_controls(struct ov965x *ov965x) { … } /* * V4L2 subdev video and pad level operations */ static void ov965x_get_default_format(struct v4l2_mbus_framefmt *mf) { … } static int ov965x_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { … } static int ov965x_enum_frame_sizes(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { … } static int ov965x_get_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_interval *fi) { … } static int __ov965x_set_frame_interval(struct ov965x *ov965x, struct v4l2_subdev_frame_interval *fi) { … } static int ov965x_set_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_interval *fi) { … } static int ov965x_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static void __ov965x_try_frame_size(struct v4l2_mbus_framefmt *mf, const struct ov965x_framesize **size) { … } static int ov965x_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int ov965x_set_frame_size(struct ov965x *ov965x) { … } static int __ov965x_set_params(struct ov965x *ov965x) { … } static int ov965x_s_stream(struct v4l2_subdev *sd, int on) { … } /* * V4L2 subdev internal operations */ static int ov965x_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { … } static const struct v4l2_subdev_pad_ops ov965x_pad_ops = …; static const struct v4l2_subdev_video_ops ov965x_video_ops = …; static const struct v4l2_subdev_internal_ops ov965x_sd_internal_ops = …; static const struct v4l2_subdev_core_ops ov965x_core_ops = …; static const struct v4l2_subdev_ops ov965x_subdev_ops = …; static int ov965x_configure_gpios(struct ov965x *ov965x) { … } static int ov965x_detect_sensor(struct v4l2_subdev *sd) { … } static int ov965x_probe(struct i2c_client *client) { … } static void ov965x_remove(struct i2c_client *client) { … } static const struct i2c_device_id ov965x_id[] = …; MODULE_DEVICE_TABLE(i2c, ov965x_id); #if IS_ENABLED(CONFIG_OF) static const struct of_device_id ov965x_of_match[] = …; MODULE_DEVICE_TABLE(of, ov965x_of_match); #endif static struct i2c_driver ov965x_i2c_driver = …; module_i2c_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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