/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics * Digitizer with Horizontal PLL registers * * Copyright (C) 2009 Texas Instruments Inc * Author: Santiago Nunez-Corrales <[email protected]> * * This code is partially based upon the TVP5150 driver * written by Mauro Carvalho Chehab <[email protected]>, * the TVP514x driver written by Vaibhav Hiremath <[email protected]> * and the TVP7002 driver in the TI LSP 2.10.00.14 */ /* Naming conventions * ------------------ * * FDBK: Feedback * DIV: Divider * CTL: Control * SEL: Select * IN: Input * OUT: Output * R: Red * G: Green * B: Blue * OFF: Offset * THRS: Threshold * DGTL: Digital * LVL: Level * PWR: Power * MVIS: Macrovision * W: Width * H: Height * ALGN: Alignment * CLK: Clocks * TOL: Tolerance * BWTH: Bandwidth * COEF: Coefficient * STAT: Status * AUTO: Automatic * FLD: Field * L: Line */ #define TVP7002_CHIP_REV … #define TVP7002_HPLL_FDBK_DIV_MSBS … #define TVP7002_HPLL_FDBK_DIV_LSBS … #define TVP7002_HPLL_CRTL … #define TVP7002_HPLL_PHASE_SEL … #define TVP7002_CLAMP_START … #define TVP7002_CLAMP_W … #define TVP7002_HSYNC_OUT_W … #define TVP7002_B_FINE_GAIN … #define TVP7002_G_FINE_GAIN … #define TVP7002_R_FINE_GAIN … #define TVP7002_B_FINE_OFF_MSBS … #define TVP7002_G_FINE_OFF_MSBS … #define TVP7002_R_FINE_OFF_MSBS … #define TVP7002_SYNC_CTL_1 … #define TVP7002_HPLL_AND_CLAMP_CTL … #define TVP7002_SYNC_ON_G_THRS … #define TVP7002_SYNC_SEPARATOR_THRS … #define TVP7002_HPLL_PRE_COAST … #define TVP7002_HPLL_POST_COAST … #define TVP7002_SYNC_DETECT_STAT … #define TVP7002_OUT_FORMATTER … #define TVP7002_MISC_CTL_1 … #define TVP7002_MISC_CTL_2 … #define TVP7002_MISC_CTL_3 … #define TVP7002_IN_MUX_SEL_1 … #define TVP7002_IN_MUX_SEL_2 … #define TVP7002_B_AND_G_COARSE_GAIN … #define TVP7002_R_COARSE_GAIN … #define TVP7002_FINE_OFF_LSBS … #define TVP7002_B_COARSE_OFF … #define TVP7002_G_COARSE_OFF … #define TVP7002_R_COARSE_OFF … #define TVP7002_HSOUT_OUT_START … #define TVP7002_MISC_CTL_4 … #define TVP7002_B_DGTL_ALC_OUT_LSBS … #define TVP7002_G_DGTL_ALC_OUT_LSBS … #define TVP7002_R_DGTL_ALC_OUT_LSBS … #define TVP7002_AUTO_LVL_CTL_ENABLE … #define TVP7002_DGTL_ALC_OUT_MSBS … #define TVP7002_AUTO_LVL_CTL_FILTER … /* Reserved 0x29*/ #define TVP7002_FINE_CLAMP_CTL … #define TVP7002_PWR_CTL … #define TVP7002_ADC_SETUP … #define TVP7002_COARSE_CLAMP_CTL … #define TVP7002_SOG_CLAMP … #define TVP7002_RGB_COARSE_CLAMP_CTL … #define TVP7002_SOG_COARSE_CLAMP_CTL … #define TVP7002_ALC_PLACEMENT … /* Reserved 0x32 */ /* Reserved 0x33 */ #define TVP7002_MVIS_STRIPPER_W … #define TVP7002_VSYNC_ALGN … #define TVP7002_SYNC_BYPASS … #define TVP7002_L_FRAME_STAT_LSBS … #define TVP7002_L_FRAME_STAT_MSBS … #define TVP7002_CLK_L_STAT_LSBS … #define TVP7002_CLK_L_STAT_MSBS … #define TVP7002_HSYNC_W … #define TVP7002_VSYNC_W … #define TVP7002_L_LENGTH_TOL … /* Reserved 0x3e */ #define TVP7002_VIDEO_BWTH_CTL … #define TVP7002_AVID_START_PIXEL_LSBS … #define TVP7002_AVID_START_PIXEL_MSBS … #define TVP7002_AVID_STOP_PIXEL_LSBS … #define TVP7002_AVID_STOP_PIXEL_MSBS … #define TVP7002_VBLK_F_0_START_L_OFF … #define TVP7002_VBLK_F_1_START_L_OFF … #define TVP7002_VBLK_F_0_DURATION … #define TVP7002_VBLK_F_1_DURATION … #define TVP7002_FBIT_F_0_START_L_OFF … #define TVP7002_FBIT_F_1_START_L_OFF … #define TVP7002_YUV_Y_G_COEF_LSBS … #define TVP7002_YUV_Y_G_COEF_MSBS … #define TVP7002_YUV_Y_B_COEF_LSBS … #define TVP7002_YUV_Y_B_COEF_MSBS … #define TVP7002_YUV_Y_R_COEF_LSBS … #define TVP7002_YUV_Y_R_COEF_MSBS … #define TVP7002_YUV_U_G_COEF_LSBS … #define TVP7002_YUV_U_G_COEF_MSBS … #define TVP7002_YUV_U_B_COEF_LSBS … #define TVP7002_YUV_U_B_COEF_MSBS … #define TVP7002_YUV_U_R_COEF_LSBS … #define TVP7002_YUV_U_R_COEF_MSBS … #define TVP7002_YUV_V_G_COEF_LSBS … #define TVP7002_YUV_V_G_COEF_MSBS … #define TVP7002_YUV_V_B_COEF_LSBS … #define TVP7002_YUV_V_B_COEF_MSBS … #define TVP7002_YUV_V_R_COEF_LSBS … #define TVP7002_YUV_V_R_COEF_MSBS …
Codebase Browser
linux