/* Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Trident Microsystems nor Hauppauge Computer Works nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. DRXJ specific header file Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen */ #ifndef __DRXJ_H__ #define __DRXJ_H__ /*------------------------------------------------------------------------- INCLUDES -------------------------------------------------------------------------*/ #include "drx_driver.h" #include "drx_dap_fasi.h" /* Check DRX-J specific dap condition */ /* Multi master mode and short addr format only will not work. RMW, CRC reset, broadcast and switching back to single master mode cannot be done with short addr only in multi master mode. */ #if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) #error "Multi master mode and short addressing only is an illegal combination" *; /* Generate a fatal compiler error to make sure it stops here, this is necessary because not all compilers stop after a #error. */ #endif /*------------------------------------------------------------------------- TYPEDEFS -------------------------------------------------------------------------*/ /*============================================================================*/ /*============================================================================*/ /*== code support ============================================================*/ /*============================================================================*/ /*============================================================================*/ /*============================================================================*/ /*============================================================================*/ /*== SCU cmd if =============================================================*/ /*============================================================================*/ /*============================================================================*/ struct drxjscu_cmd { … }; /*============================================================================*/ /*============================================================================*/ /*== CTRL CFG related data structures ========================================*/ /*============================================================================*/ /*============================================================================*/ /* extra intermediate lock state for VSB,QAM,NTSC */ #define DRXJ_DEMOD_LOCK … /* OOB lock states */ #define DRXJ_OOB_AGC_LOCK … #define DRXJ_OOB_SYNC_LOCK … /* Intermediate powermodes for DRXJ */ #define DRXJ_POWER_DOWN_MAIN_PATH … #define DRXJ_POWER_DOWN_CORE … #define DRXJ_POWER_DOWN_PLL … /* supstition for GPIO FNC mux */ #define APP_O … /*#define DRX_CTRL_BASE (0x0000)*/ #define DRXJ_CTRL_CFG_BASE … enum drxj_cfg_type { … }; /* * /enum drxj_cfg_smart_ant_io * smart antenna i/o. */ enum drxj_cfg_smart_ant_io { … }; /* * /struct drxj_cfg_smart_ant * Set smart antenna. */ struct drxj_cfg_smart_ant { … }; /* * /struct DRXJAGCSTATUS_t * AGC status information from the DRXJ-IQM-AF. */ struct drxj_agc_status { … }; /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ /* * /enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. */ enum drxj_agc_ctrl_mode { … }; /* * /struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. */ struct drxj_cfg_agc { … }; /* DRXJ_CFG_PRE_SAW */ /* * /struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. */ struct drxj_cfg_pre_saw { … }; /* DRXJ_CFG_AFE_GAIN */ /* * /struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). */ struct drxj_cfg_afe_gain { … }; /* * /struct drxjrs_errors * Available failure information in DRXJ_FEC_RS. * * Container for errors that are received in the most recently finished measurement period * */ struct drxjrs_errors { … }; /* * /struct drxj_cfg_vsb_misc * symbol error rate */ struct drxj_cfg_vsb_misc { … }; /* * /enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. * */ enum drxj_mpeg_start_width { … }; /* * /enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. * */ enum drxj_mpeg_output_clock_rate { … }; /* * /struct DRXJCfgMisc_t * Change TEI bit of MPEG output * reverse MPEG output bit order * set MPEG output clock rate */ struct drxj_cfg_mpeg_output_misc { … }; /* * /enum drxj_xtal_freq * Supported external crystal reference frequency. */ enum drxj_xtal_freq { … }; /* * /enum drxj_xtal_freq * Supported external crystal reference frequency. */ enum drxji2c_speed { … }; /* * /struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal * reference frequency, I2C speed, etc... */ struct drxj_cfg_hw_cfg { … }; /* * DRXJ_CFG_ATV_MISC */ struct drxj_cfg_atv_misc { … }; /* * struct drxj_cfg_oob_misc */ #define DRXJ_OOB_STATE_RESET … #define DRXJ_OOB_STATE_AGN_HUNT … #define DRXJ_OOB_STATE_DGN_HUNT … #define DRXJ_OOB_STATE_AGC_HUNT … #define DRXJ_OOB_STATE_FRQ_HUNT … #define DRXJ_OOB_STATE_PHA_HUNT … #define DRXJ_OOB_STATE_TIM_HUNT … #define DRXJ_OOB_STATE_EQU_HUNT … #define DRXJ_OOB_STATE_EQT_HUNT … #define DRXJ_OOB_STATE_SYNC … struct drxj_cfg_oob_misc { … }; /* * Index of in array of coef */ enum drxj_cfg_oob_lo_power { … }; /* * DRXJ_CFG_ATV_EQU_COEF */ struct drxj_cfg_atv_equ_coef { … }; /* * Index of in array of coef */ enum drxj_coef_array_index { … }; /* * DRXJ_CFG_ATV_OUTPUT */ /* * /enum DRXJAttenuation_t * Attenuation setting for SIF AGC. * */ enum drxjsif_attenuation { … }; /* * /struct drxj_cfg_atv_output * SIF attenuation setting. * */ struct drxj_cfg_atv_output { … }; /* DRXJ_CFG_ATV_AGC_STATUS (get only) */ /* TODO : AFE interface not yet finished, subject to change */ struct drxj_cfg_atv_agc_status { … }; /*============================================================================*/ /*============================================================================*/ /*== CTRL related data structures ============================================*/ /*============================================================================*/ /*============================================================================*/ /* NONE */ /*============================================================================*/ /*============================================================================*/ /*========================================*/ /* * /struct struct drxj_data * DRXJ specific attributes. * * Global data container for DRXJ specific data. * */ struct drxj_data { … }; /*------------------------------------------------------------------------- Access MACROS -------------------------------------------------------------------------*/ /* * \brief Compilable references to attributes * \param d pointer to demod instance * * Used as main reference to an attribute field. * Can be used by both macro implementation and function implementation. * These macros are defined to avoid duplication of code in macro and function * definitions that handle access of demod common or extended attributes. * */ #define DRXJ_ATTR_BTSC_DETECT(d) … /*------------------------------------------------------------------------- DEFINES -------------------------------------------------------------------------*/ /* * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * * For NTSC standard. * NTSC channels are listed by their picture carrier frequency (Fpc). * The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. * In case the tuner module is not used the DRX-J requires that the tuner is * tuned to the centre frequency of the channel: * * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET * */ #define DRXJ_NTSC_CARRIER_FREQ_OFFSET … /* * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * * For PAL/SECAM - BG standard. This define is needed in case the tuner module * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). * The DRX-J requires that the tuner is tuned to: * Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET * * In case the tuner module is used the drxdriver takes care of this. * In case the tuner module is NOT used the application programmer must take * care of this. * */ #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET … /* * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * * For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). * The DRX-J requires that the tuner is tuned to: * Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET * * In case the tuner module is used the drxdriver takes care of this. * In case the tuner module is NOT used the application programmer must take * care of this. * */ #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET … /* * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET * \brief Offset from picture carrier to centre frequency in kHz, in RF domain * * For PAL/SECAM - LP standard. This define is needed in case the tuner module * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). * The DRX-J requires that the tuner is tuned to: * Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET * * In case the tuner module is used the drxdriver takes care of this. * In case the tuner module is NOT used the application programmer must take * care of this. */ #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET … /* * \def DRXJ_FM_CARRIER_FREQ_OFFSET * \brief Offset from sound carrier to centre frequency in kHz, in RF domain * * For FM standard. * FM channels are listed by their sound carrier frequency (Fsc). * The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as * input. * In case the tuner module is not used the DRX-J requires that the tuner is * tuned to the Ffm frequency of the channel. * * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET * */ #define DRXJ_FM_CARRIER_FREQ_OFFSET … /* Revision types -------------------------------------------------------*/ #define DRXJ_TYPE_ID … /* Macros ---------------------------------------------------------------*/ /* Convert OOB lock status to string */ #define DRXJ_STR_OOB_LOCKSTATUS(x) … #endif /* __DRXJ_H__ */
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