/* SPDX-License-Identifier: GPL-2.0-only */ /* * dib3000mb_priv.h * * Copyright (C) 2004 Patrick Boettcher ([email protected]) * * for more information see dib3000mb.c . */ #ifndef __DIB3000MB_PRIV_H_INCLUDED__ #define __DIB3000MB_PRIV_H_INCLUDED__ /* handy shortcuts */ #define rd(reg) … #define wr(reg,val) … #define wr_foreach(a,v) … #define set_or(reg,val) … #define set_and(reg,val) … /* debug */ #define dprintk(level, fmt, arg...) … /* mask for enabling a specific pid for the pid_filter */ #define DIB3000_ACTIVATE_PID_FILTERING … /* common values for tuning */ #define DIB3000_ALPHA_0 … #define DIB3000_ALPHA_1 … #define DIB3000_ALPHA_2 … #define DIB3000_ALPHA_4 … #define DIB3000_CONSTELLATION_QPSK … #define DIB3000_CONSTELLATION_16QAM … #define DIB3000_CONSTELLATION_64QAM … #define DIB3000_GUARD_TIME_1_32 … #define DIB3000_GUARD_TIME_1_16 … #define DIB3000_GUARD_TIME_1_8 … #define DIB3000_GUARD_TIME_1_4 … #define DIB3000_TRANSMISSION_MODE_2K … #define DIB3000_TRANSMISSION_MODE_8K … #define DIB3000_SELECT_LP … #define DIB3000_SELECT_HP … #define DIB3000_FEC_1_2 … #define DIB3000_FEC_2_3 … #define DIB3000_FEC_3_4 … #define DIB3000_FEC_5_6 … #define DIB3000_FEC_7_8 … #define DIB3000_HRCH_OFF … #define DIB3000_HRCH_ON … #define DIB3000_DDS_INVERSION_OFF … #define DIB3000_DDS_INVERSION_ON … #define DIB3000_TUNER_WRITE_ENABLE(a) … #define DIB3000_TUNER_WRITE_DISABLE(a) … #define DIB3000_REG_MANUFACTOR_ID … #define DIB3000_I2C_ID_DIBCOM … #define DIB3000_REG_DEVICE_ID … #define DIB3000MB_DEVICE_ID … #define DIB3000MC_DEVICE_ID … #define DIB3000P_DEVICE_ID … /* frontend state */ struct dib3000_state { … }; /* register addresses and some of their default values */ /* restart subsystems */ #define DIB3000MB_REG_RESTART … #define DIB3000MB_RESTART_OFF … #define DIB3000MB_RESTART_AUTO_SEARCH … #define DIB3000MB_RESTART_CTRL … #define DIB3000MB_RESTART_AGC … /* FFT size */ #define DIB3000MB_REG_FFT … /* Guard time */ #define DIB3000MB_REG_GUARD_TIME … /* QAM */ #define DIB3000MB_REG_QAM … /* Alpha coefficient high priority Viterbi algorithm */ #define DIB3000MB_REG_VIT_ALPHA … /* spectrum inversion */ #define DIB3000MB_REG_DDS_INV … /* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */ #define DIB3000MB_REG_DDS_FREQ_MSB … #define DIB3000MB_REG_DDS_FREQ_LSB … #define DIB3000MB_DDS_FREQ_MSB … #define DIB3000MB_DDS_FREQ_LSB … /* timing frequency (carrier spacing) */ static u16 dib3000mb_reg_timing_freq[] = …; static u16 dib3000mb_timing_freq[][2] = …; /* impulse noise parameter */ /* 36 ??? */ static u16 dib3000mb_reg_impulse_noise[] = …; enum dib3000mb_impulse_noise_type { … }; static u16 dib3000mb_impulse_noise_values[][5] = …; /* * Dual Automatic-Gain-Control * - gains RF in tuner (AGC1) * - gains IF after filtering (AGC2) */ /* also from 16 to 18 */ static u16 dib3000mb_reg_agc_gain[] = …; static u16 dib3000mb_default_agc_gain[] = …; /* IF ??? */ /* phase noise */ /* 36 is set when setting the impulse noise */ static u16 dib3000mb_reg_phase_noise[] = …; static u16 dib3000mb_default_noise_phase[] = …; /* lock duration */ static u16 dib3000mb_reg_lock_duration[] = …; static u16 dib3000mb_default_lock_duration[] = …; /* AGC loop bandwidth */ static u16 dib3000mb_reg_agc_bandwidth[] = …; static u16 dib3000mb_agc_bandwidth_low[] = …; static u16 dib3000mb_agc_bandwidth_high[] = …; /* * lock0 definition (coff_lock) */ #define DIB3000MB_REG_LOCK0_MASK … #define DIB3000MB_LOCK0_DEFAULT … /* * lock1 definition (cpil_lock) * for auto search * which values hide behind the lock masks */ #define DIB3000MB_REG_LOCK1_MASK … #define DIB3000MB_LOCK1_SEARCH_4 … #define DIB3000MB_LOCK1_SEARCH_2048 … #define DIB3000MB_LOCK1_DEFAULT … /* * lock2 definition (fec_lock) */ #define DIB3000MB_REG_LOCK2_MASK … #define DIB3000MB_LOCK2_DEFAULT … /* * SEQ ? what was that again ... :) * changes when, inversion, guard time and fft is * either automatically detected or not */ #define DIB3000MB_REG_SEQ … /* bandwidth */ static u16 dib3000mb_reg_bandwidth[] = …; static u16 dib3000mb_bandwidth_6mhz[] = …; static u16 dib3000mb_bandwidth_7mhz[] = …; static u16 dib3000mb_bandwidth_8mhz[] = …; #define DIB3000MB_REG_UNK_68 … #define DIB3000MB_UNK_68 … #define DIB3000MB_REG_UNK_69 … #define DIB3000MB_UNK_69 … #define DIB3000MB_REG_UNK_71 … #define DIB3000MB_UNK_71 … #define DIB3000MB_REG_UNK_77 … #define DIB3000MB_UNK_77 … #define DIB3000MB_REG_UNK_78 … #define DIB3000MB_UNK_78 … /* isi */ #define DIB3000MB_REG_ISI … #define DIB3000MB_ISI_ACTIVATE … #define DIB3000MB_ISI_INHIBIT … /* sync impovement */ #define DIB3000MB_REG_SYNC_IMPROVEMENT … #define DIB3000MB_SYNC_IMPROVE_2K_1_8 … #define DIB3000MB_SYNC_IMPROVE_DEFAULT … /* phase noise compensation inhibition */ #define DIB3000MB_REG_PHASE_NOISE … #define DIB3000MB_PHASE_NOISE_DEFAULT … #define DIB3000MB_REG_UNK_92 … #define DIB3000MB_UNK_92 … #define DIB3000MB_REG_UNK_96 … #define DIB3000MB_UNK_96 … #define DIB3000MB_REG_UNK_97 … #define DIB3000MB_UNK_97 … /* mobile mode ??? */ #define DIB3000MB_REG_MOBILE_MODE … #define DIB3000MB_MOBILE_MODE_ON … #define DIB3000MB_MOBILE_MODE_OFF … #define DIB3000MB_REG_UNK_106 … #define DIB3000MB_UNK_106 … #define DIB3000MB_REG_UNK_107 … #define DIB3000MB_UNK_107 … #define DIB3000MB_REG_UNK_108 … #define DIB3000MB_UNK_108 … /* fft */ #define DIB3000MB_REG_UNK_121 … #define DIB3000MB_UNK_121_2K … #define DIB3000MB_UNK_121_DEFAULT … #define DIB3000MB_REG_UNK_122 … #define DIB3000MB_UNK_122 … /* QAM for mobile mode */ #define DIB3000MB_REG_MOBILE_MODE_QAM … #define DIB3000MB_MOBILE_MODE_QAM_64 … #define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 … #define DIB3000MB_MOBILE_MODE_QAM_OFF … /* * data diversity when having more than one chip on-board * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY */ #define DIB3000MB_REG_DATA_IN_DIVERSITY … #define DIB3000MB_DATA_DIVERSITY_IN_OFF … #define DIB3000MB_DATA_DIVERSITY_IN_ON … /* vit hrch */ #define DIB3000MB_REG_VIT_HRCH … /* vit code rate */ #define DIB3000MB_REG_VIT_CODE_RATE … /* vit select hp */ #define DIB3000MB_REG_VIT_HP … /* time frame for Bit-Error-Rate calculation */ #define DIB3000MB_REG_BERLEN … #define DIB3000MB_BERLEN_LONG … #define DIB3000MB_BERLEN_DEFAULT … #define DIB3000MB_BERLEN_MEDIUM … #define DIB3000MB_BERLEN_SHORT … /* 142 - 152 FIFO parameters * which is what ? */ #define DIB3000MB_REG_FIFO_142 … #define DIB3000MB_FIFO_142 … /* MPEG2 TS output mode */ #define DIB3000MB_REG_MPEG2_OUT_MODE … #define DIB3000MB_MPEG2_OUT_MODE_204 … #define DIB3000MB_MPEG2_OUT_MODE_188 … #define DIB3000MB_REG_PID_PARSE … #define DIB3000MB_PID_PARSE_INHIBIT … #define DIB3000MB_PID_PARSE_ACTIVATE … #define DIB3000MB_REG_FIFO … #define DIB3000MB_FIFO_INHIBIT … #define DIB3000MB_FIFO_ACTIVATE … #define DIB3000MB_REG_FIFO_146 … #define DIB3000MB_FIFO_146 … #define DIB3000MB_REG_FIFO_147 … #define DIB3000MB_FIFO_147 … /* * pidfilter * it is not a hardware pidfilter but a filter which drops all pids * except the ones set. Necessary because of the limited USB1.1 bandwidth. * regs 153-168 */ #define DIB3000MB_REG_FIRST_PID … #define DIB3000MB_NUM_PIDS … /* * output mode * USB devices have to use 'slave'-mode * see also DIB3000MB_REG_ELECT_OUT_MODE */ #define DIB3000MB_REG_OUTPUT_MODE … #define DIB3000MB_OUTPUT_MODE_GATED_CLK … #define DIB3000MB_OUTPUT_MODE_CONT_CLK … #define DIB3000MB_OUTPUT_MODE_SERIAL … #define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY … #define DIB3000MB_OUTPUT_MODE_SLAVE … /* irq event mask */ #define DIB3000MB_REG_IRQ_EVENT_MASK … #define DIB3000MB_IRQ_EVENT_MASK … /* filter coefficients */ static u16 dib3000mb_reg_filter_coeffs[] = …; static u16 dib3000mb_filter_coeffs[] = …; /* * mobile algorithm (when you are moving with your device) * but not faster than 90 km/h */ #define DIB3000MB_REG_MOBILE_ALGO … #define DIB3000MB_MOBILE_ALGO_ON … #define DIB3000MB_MOBILE_ALGO_OFF … /* multiple demodulators algorithm */ #define DIB3000MB_REG_MULTI_DEMOD_MSB … #define DIB3000MB_REG_MULTI_DEMOD_LSB … /* terminator, no more demods */ #define DIB3000MB_MULTI_DEMOD_MSB … #define DIB3000MB_MULTI_DEMOD_LSB … /* bring the device into a known */ #define DIB3000MB_REG_RESET_DEVICE … #define DIB3000MB_RESET_DEVICE … #define DIB3000MB_RESET_DEVICE_RST … /* hardware clock configuration */ #define DIB3000MB_REG_CLOCK … #define DIB3000MB_CLOCK_DEFAULT … #define DIB3000MB_CLOCK_DIVERSITY … /* power down config */ #define DIB3000MB_REG_POWER_CONTROL … #define DIB3000MB_POWER_DOWN … #define DIB3000MB_POWER_UP … /* electrical output mode */ #define DIB3000MB_REG_ELECT_OUT_MODE … #define DIB3000MB_ELECT_OUT_MODE_OFF … #define DIB3000MB_ELECT_OUT_MODE_ON … /* set the tuner i2c address */ #define DIB3000MB_REG_TUNER … /* monitoring registers (read only) */ /* agc loop locked (size: 1) */ #define DIB3000MB_REG_AGC_LOCK … /* agc power (size: 16) */ #define DIB3000MB_REG_AGC_POWER … /* agc1 value (16) */ #define DIB3000MB_REG_AGC1_VALUE … /* agc2 value (16) */ #define DIB3000MB_REG_AGC2_VALUE … /* total RF power (16), can be used for signal strength */ #define DIB3000MB_REG_RF_POWER … /* dds_frequency with offset (24) */ #define DIB3000MB_REG_DDS_VALUE_MSB … #define DIB3000MB_REG_DDS_VALUE_LSB … /* timing offset signed (24) */ #define DIB3000MB_REG_TIMING_OFFSET_MSB … #define DIB3000MB_REG_TIMING_OFFSET_LSB … /* fft start position (13) */ #define DIB3000MB_REG_FFT_WINDOW_POS … /* carriers locked (1) */ #define DIB3000MB_REG_CARRIER_LOCK … /* noise power (24) */ #define DIB3000MB_REG_NOISE_POWER_MSB … #define DIB3000MB_REG_NOISE_POWER_LSB … #define DIB3000MB_REG_MOBILE_NOISE_MSB … #define DIB3000MB_REG_MOBILE_NOISE_LSB … /* * signal power (16), this and the above can be * used to calculate the signal/noise - ratio */ #define DIB3000MB_REG_SIGNAL_POWER … /* mer (24) */ #define DIB3000MB_REG_MER_MSB … #define DIB3000MB_REG_MER_LSB … /* * Transmission Parameter Signalling (TPS) * the following registers can be used to get TPS-information. * The values are according to the DVB-T standard. */ /* TPS locked (1) */ #define DIB3000MB_REG_TPS_LOCK … /* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */ #define DIB3000MB_REG_TPS_QAM … /* hierarchy from TPS (1) */ #define DIB3000MB_REG_TPS_HRCH … /* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */ #define DIB3000MB_REG_TPS_VIT_ALPHA … /* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */ #define DIB3000MB_REG_TPS_CODE_RATE_HP … /* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */ #define DIB3000MB_REG_TPS_CODE_RATE_LP … /* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */ #define DIB3000MB_REG_TPS_GUARD_TIME … /* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */ #define DIB3000MB_REG_TPS_FFT … /* cell id from TPS (16) */ #define DIB3000MB_REG_TPS_CELL_ID … /* TPS (68) */ #define DIB3000MB_REG_TPS_1 … #define DIB3000MB_REG_TPS_2 … #define DIB3000MB_REG_TPS_3 … #define DIB3000MB_REG_TPS_4 … #define DIB3000MB_REG_TPS_5 … /* bit error rate (before RS correction) (21) */ #define DIB3000MB_REG_BER_MSB … #define DIB3000MB_REG_BER_LSB … /* packet error rate (uncorrected TS packets) (16) */ #define DIB3000MB_REG_PACKET_ERROR_RATE … /* uncorrected packet count (16) */ #define DIB3000MB_REG_UNC … /* viterbi locked (1) */ #define DIB3000MB_REG_VIT_LCK … /* viterbi inidcator (16) */ #define DIB3000MB_REG_VIT_INDICATOR … /* transport stream sync lock (1) */ #define DIB3000MB_REG_TS_SYNC_LOCK … /* transport stream RS lock (1) */ #define DIB3000MB_REG_TS_RS_LOCK … /* lock mask 0 value (1) */ #define DIB3000MB_REG_LOCK0_VALUE … /* lock mask 1 value (1) */ #define DIB3000MB_REG_LOCK1_VALUE … /* lock mask 2 value (1) */ #define DIB3000MB_REG_LOCK2_VALUE … /* interrupt pending for auto search */ #define DIB3000MB_REG_AS_IRQ_PENDING … #endif
Codebase Browser
linux