linux/drivers/media/dvb-frontends/drxd_map_firm.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * drx3973d_map_firm.h
 *
 * Copyright (C) 2006-2007 Micronas
 */

#ifndef __DRX3973D_MAP__H__
#define __DRX3973D_MAP__H__

/*
 * Note: originally, this file contained 12000+ lines of data
 * Probably a few lines for every firwmare assembler instruction. However,
 * only a few defines were actually used. So, removed all uneeded lines.
 * If ever needed, the other lines can be easily obtained via git history.
 */

#define HI_COMM_EXEC__A
#define HI_COMM_MB__A
#define HI_CT_REG_COMM_STATE__A
#define HI_RA_RAM_SRV_RES__A
#define HI_RA_RAM_SRV_CMD__A
#define HI_RA_RAM_SRV_CMD_RESET
#define HI_RA_RAM_SRV_CMD_CONFIG
#define HI_RA_RAM_SRV_CMD_EXECUTE
#define HI_RA_RAM_SRV_RST_KEY__A
#define HI_RA_RAM_SRV_RST_KEY_ACT
#define HI_RA_RAM_SRV_CFG_KEY__A
#define HI_RA_RAM_SRV_CFG_DIV__A
#define HI_RA_RAM_SRV_CFG_BDL__A
#define HI_RA_RAM_SRV_CFG_WUP__A
#define HI_RA_RAM_SRV_CFG_ACT__A
#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON
#define HI_RA_RAM_SRV_CFG_ACT_BRD__M
#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF
#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON
#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE
#define HI_RA_RAM_USR_BEGIN__A
#define HI_IF_RAM_TRP_BPT0__AX
#define HI_IF_RAM_USR_BEGIN__A
#define SC_COMM_EXEC__A
#define SC_COMM_EXEC_CTL_STOP
#define SC_COMM_STATE__A
#define SC_RA_RAM_PARAM0__A
#define SC_RA_RAM_PARAM1__A
#define SC_RA_RAM_CMD_ADDR__A
#define SC_RA_RAM_CMD__A
#define SC_RA_RAM_CMD_PROC_START
#define SC_RA_RAM_CMD_SET_PREF_PARAM
#define SC_RA_RAM_CMD_GET_OP_PARAM
#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M
#define SC_RA_RAM_LOCKTRACK_MIN
#define SC_RA_RAM_OP_PARAM_MODE_2K
#define SC_RA_RAM_OP_PARAM_MODE_8K
#define SC_RA_RAM_OP_PARAM_GUARD_32
#define SC_RA_RAM_OP_PARAM_GUARD_16
#define SC_RA_RAM_OP_PARAM_GUARD_8
#define SC_RA_RAM_OP_PARAM_GUARD_4
#define SC_RA_RAM_OP_PARAM_CONST_QPSK
#define SC_RA_RAM_OP_PARAM_CONST_QAM16
#define SC_RA_RAM_OP_PARAM_CONST_QAM64
#define SC_RA_RAM_OP_PARAM_HIER_NO
#define SC_RA_RAM_OP_PARAM_HIER_A1
#define SC_RA_RAM_OP_PARAM_HIER_A2
#define SC_RA_RAM_OP_PARAM_HIER_A4
#define SC_RA_RAM_OP_PARAM_RATE_1_2
#define SC_RA_RAM_OP_PARAM_RATE_2_3
#define SC_RA_RAM_OP_PARAM_RATE_3_4
#define SC_RA_RAM_OP_PARAM_RATE_5_6
#define SC_RA_RAM_OP_PARAM_RATE_7_8
#define SC_RA_RAM_OP_PARAM_PRIO_HI
#define SC_RA_RAM_OP_PARAM_PRIO_LO
#define SC_RA_RAM_OP_AUTO_MODE__M
#define SC_RA_RAM_OP_AUTO_GUARD__M
#define SC_RA_RAM_OP_AUTO_CONST__M
#define SC_RA_RAM_OP_AUTO_HIER__M
#define SC_RA_RAM_OP_AUTO_RATE__M
#define SC_RA_RAM_LOCK__A
#define SC_RA_RAM_LOCK_DEMOD__M
#define SC_RA_RAM_LOCK_FEC__M
#define SC_RA_RAM_LOCK_MPEG__M
#define SC_RA_RAM_BE_OPT_ENA__A
#define SC_RA_RAM_BE_OPT_ENA_CP_OPT
#define SC_RA_RAM_BE_OPT_DELAY__A
#define SC_RA_RAM_CONFIG__A
#define SC_RA_RAM_CONFIG_FR_ENABLE__M
#define SC_RA_RAM_CONFIG_FREQSCAN__M
#define SC_RA_RAM_CONFIG_SLAVE__M
#define SC_RA_RAM_IF_SAVE__AX
#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A
#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE
#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A
#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE
#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A
#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE
#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A
#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE
#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A
#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE
#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A
#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE
#define SC_RA_RAM_IR_FINE_2K_LENGTH__A
#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE
#define SC_RA_RAM_IR_FINE_2K_FREQINC__A
#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE
#define SC_RA_RAM_IR_FINE_2K_KAISINC__A
#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE
#define SC_RA_RAM_IR_FINE_8K_LENGTH__A
#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE
#define SC_RA_RAM_IR_FINE_8K_FREQINC__A
#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE
#define SC_RA_RAM_IR_FINE_8K_KAISINC__A
#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE
#define SC_RA_RAM_ECHO_SHIFT_LIM__A
#define SC_RA_RAM_SAMPLE_RATE_COUNT__A
#define SC_RA_RAM_SAMPLE_RATE_STEP__A
#define SC_RA_RAM_BAND__A
#define SC_RA_RAM_LC_ABS_2K__A
#define SC_RA_RAM_LC_ABS_2K__PRE
#define SC_RA_RAM_LC_ABS_8K__A
#define SC_RA_RAM_LC_ABS_8K__PRE
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE
#define SC_RA_RAM_DRIVER_VERSION__AX
#define SC_RA_RAM_PROC_LOCKTRACK
#define FE_COMM_EXEC__A
#define FE_AD_REG_COMM_EXEC__A
#define FE_AD_REG_FDB_IN__A
#define FE_AD_REG_PD__A
#define FE_AD_REG_INVEXT__A
#define FE_AD_REG_CLKNEG__A
#define FE_AG_REG_COMM_EXEC__A
#define FE_AG_REG_AG_MODE_LOP__A
#define FE_AG_REG_AG_MODE_LOP_MODE_4__M
#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC
#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC
#define FE_AG_REG_AG_MODE_LOP_MODE_5__M
#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
#define FE_AG_REG_AG_MODE_LOP_MODE_C__M
#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC
#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC
#define FE_AG_REG_AG_MODE_LOP_MODE_E__M
#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC
#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC
#define FE_AG_REG_AG_MODE_HIP__A
#define FE_AG_REG_AG_PGA_MODE__A
#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN
#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
#define FE_AG_REG_AG_AGC_SIO__A
#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT
#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT
#define FE_AG_REG_AG_PWD__A
#define FE_AG_REG_AG_PWD_PWD_PD2__M
#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE
#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE
#define FE_AG_REG_DCE_AUR_CNT__A
#define FE_AG_REG_DCE_RUR_CNT__A
#define FE_AG_REG_ACE_AUR_CNT__A
#define FE_AG_REG_ACE_RUR_CNT__A
#define FE_AG_REG_CDR_RUR_CNT__A
#define FE_AG_REG_EGC_RUR_CNT__A
#define FE_AG_REG_EGC_SET_LVL__A
#define FE_AG_REG_EGC_SET_LVL__M
#define FE_AG_REG_EGC_FLA_RGN__A
#define FE_AG_REG_EGC_SLO_RGN__A
#define FE_AG_REG_EGC_JMP_PSN__A
#define FE_AG_REG_EGC_FLA_INC__A
#define FE_AG_REG_EGC_FLA_DEC__A
#define FE_AG_REG_EGC_SLO_INC__A
#define FE_AG_REG_EGC_SLO_DEC__A
#define FE_AG_REG_EGC_FAS_INC__A
#define FE_AG_REG_EGC_FAS_DEC__A
#define FE_AG_REG_PM1_AGC_WRI__A
#define FE_AG_REG_PM1_AGC_WRI__M
#define FE_AG_REG_GC1_AGC_RIC__A
#define FE_AG_REG_GC1_AGC_OFF__A
#define FE_AG_REG_GC1_AGC_MAX__A
#define FE_AG_REG_GC1_AGC_MIN__A
#define FE_AG_REG_GC1_AGC_DAT__A
#define FE_AG_REG_GC1_AGC_DAT__M
#define FE_AG_REG_PM2_AGC_WRI__A
#define FE_AG_REG_IND_WIN__A
#define FE_AG_REG_IND_THD_LOL__A
#define FE_AG_REG_IND_THD_HIL__A
#define FE_AG_REG_IND_DEL__A
#define FE_AG_REG_IND_PD1_WRI__A
#define FE_AG_REG_PDA_AUR_CNT__A
#define FE_AG_REG_PDA_RUR_CNT__A
#define FE_AG_REG_PDA_AVE_DAT__A
#define FE_AG_REG_PDC_RUR_CNT__A
#define FE_AG_REG_PDC_SET_LVL__A
#define FE_AG_REG_PDC_FLA_RGN__A
#define FE_AG_REG_PDC_JMP_PSN__A
#define FE_AG_REG_PDC_FLA_STP__A
#define FE_AG_REG_PDC_SLO_STP__A
#define FE_AG_REG_PDC_PD2_WRI__A
#define FE_AG_REG_PDC_MAP_DAT__A
#define FE_AG_REG_PDC_MAX__A
#define FE_AG_REG_TGA_AUR_CNT__A
#define FE_AG_REG_TGA_RUR_CNT__A
#define FE_AG_REG_TGA_AVE_DAT__A
#define FE_AG_REG_TGC_RUR_CNT__A
#define FE_AG_REG_TGC_SET_LVL__A
#define FE_AG_REG_TGC_SET_LVL__M
#define FE_AG_REG_TGC_FLA_RGN__A
#define FE_AG_REG_TGC_JMP_PSN__A
#define FE_AG_REG_TGC_FLA_STP__A
#define FE_AG_REG_TGC_SLO_STP__A
#define FE_AG_REG_TGC_MAP_DAT__A
#define FE_AG_REG_FGA_AUR_CNT__A
#define FE_AG_REG_FGA_RUR_CNT__A
#define FE_AG_REG_FGM_WRI__A
#define FE_AG_REG_BGC_FGC_WRI__A
#define FE_AG_REG_BGC_CGC_WRI__A
#define FE_FS_REG_COMM_EXEC__A
#define FE_FS_REG_ADD_INC_LOP__A
#define FE_FD_REG_COMM_EXEC__A
#define FE_FD_REG_SCL__A
#define FE_FD_REG_MAX_LEV__A
#define FE_FD_REG_NR__A
#define FE_FD_REG_MEAS_VAL__A
#define FE_IF_REG_COMM_EXEC__A
#define FE_IF_REG_INCR0__A
#define FE_IF_REG_INCR0__W
#define FE_IF_REG_INCR0__M
#define FE_IF_REG_INCR1__A
#define FE_IF_REG_INCR1__M
#define FE_CF_REG_COMM_EXEC__A
#define FE_CF_REG_SCL__A
#define FE_CF_REG_MAX_LEV__A
#define FE_CF_REG_NR__A
#define FE_CF_REG_IMP_VAL__A
#define FE_CF_REG_MEAS_VAL__A
#define FE_CU_REG_COMM_EXEC__A
#define FE_CU_REG_FRM_CNT_RST__A
#define FE_CU_REG_FRM_CNT_STR__A
#define FT_COMM_EXEC__A
#define FT_REG_COMM_EXEC__A
#define CP_COMM_EXEC__A
#define CP_REG_COMM_EXEC__A
#define CP_REG_INTERVAL__A
#define CP_REG_BR_SPL_OFFSET__A
#define CP_REG_BR_STR_DEL__A
#define CP_REG_RT_ANG_INC0__A
#define CP_REG_RT_ANG_INC1__A
#define CP_REG_RT_DETECT_ENA__A
#define CP_REG_RT_DETECT_TRH__A
#define CP_REG_RT_EXP_MARG__A
#define CP_REG_AC_NEXP_OFFS__A
#define CP_REG_AC_AVER_POW__A
#define CP_REG_AC_MAX_POW__A
#define CP_REG_AC_WEIGHT_MAN__A
#define CP_REG_AC_WEIGHT_EXP__A
#define CP_REG_AC_AMP_MODE__A
#define CP_REG_AC_AMP_FIX__A
#define CP_REG_AC_ANG_MODE__A
#define CE_COMM_EXEC__A
#define CE_REG_COMM_EXEC__A
#define CE_REG_TAPSET__A
#define CE_REG_AVG_POW__A
#define CE_REG_MAX_POW__A
#define CE_REG_ATT__A
#define CE_REG_NRED__A
#define CE_REG_NE_ERR_SELECT__A
#define CE_REG_NE_TD_CAL__A
#define CE_REG_NE_MIXAVG__A
#define CE_REG_NE_NUPD_OFS__A
#define CE_REG_PE_NEXP_OFFS__A
#define CE_REG_PE_TIMESHIFT__A
#define CE_REG_TP_A0_TAP_NEW__A
#define CE_REG_TP_A0_TAP_NEW_VALID__A
#define CE_REG_TP_A0_MU_LMS_STEP__A
#define CE_REG_TP_A1_TAP_NEW__A
#define CE_REG_TP_A1_TAP_NEW_VALID__A
#define CE_REG_TP_A1_MU_LMS_STEP__A
#define CE_REG_TI_NEXP_OFFS__A
#define CE_REG_FI_SHT_INCR__A
#define CE_REG_FI_EXP_NORM__A
#define CE_REG_IR_INPUTSEL__A
#define CE_REG_IR_STARTPOS__A
#define CE_REG_IR_NEXP_THRES__A
#define CE_REG_FR_TREAL00__A
#define CE_REG_FR_TIMAG00__A
#define CE_REG_FR_TREAL01__A
#define CE_REG_FR_TIMAG01__A
#define CE_REG_FR_TREAL02__A
#define CE_REG_FR_TIMAG02__A
#define CE_REG_FR_TREAL03__A
#define CE_REG_FR_TIMAG03__A
#define CE_REG_FR_TREAL04__A
#define CE_REG_FR_TIMAG04__A
#define CE_REG_FR_TREAL05__A
#define CE_REG_FR_TIMAG05__A
#define CE_REG_FR_TREAL06__A
#define CE_REG_FR_TIMAG06__A
#define CE_REG_FR_TREAL07__A
#define CE_REG_FR_TIMAG07__A
#define CE_REG_FR_TREAL08__A
#define CE_REG_FR_TIMAG08__A
#define CE_REG_FR_TREAL09__A
#define CE_REG_FR_TIMAG09__A
#define CE_REG_FR_TREAL10__A
#define CE_REG_FR_TIMAG10__A
#define CE_REG_FR_TREAL11__A
#define CE_REG_FR_TIMAG11__A
#define CE_REG_FR_MID_TAP__A
#define CE_REG_FR_SQS_G00__A
#define CE_REG_FR_SQS_G01__A
#define CE_REG_FR_SQS_G02__A
#define CE_REG_FR_SQS_G03__A
#define CE_REG_FR_SQS_G04__A
#define CE_REG_FR_SQS_G05__A
#define CE_REG_FR_SQS_G06__A
#define CE_REG_FR_SQS_G07__A
#define CE_REG_FR_SQS_G08__A
#define CE_REG_FR_SQS_G09__A
#define CE_REG_FR_SQS_G10__A
#define CE_REG_FR_SQS_G11__A
#define CE_REG_FR_SQS_G12__A
#define CE_REG_FR_RIO_G00__A
#define CE_REG_FR_RIO_G01__A
#define CE_REG_FR_RIO_G02__A
#define CE_REG_FR_RIO_G03__A
#define CE_REG_FR_RIO_G04__A
#define CE_REG_FR_RIO_G05__A
#define CE_REG_FR_RIO_G06__A
#define CE_REG_FR_RIO_G07__A
#define CE_REG_FR_RIO_G08__A
#define CE_REG_FR_RIO_G09__A
#define CE_REG_FR_RIO_G10__A
#define CE_REG_FR_MODE__A
#define CE_REG_FR_SQS_TRH__A
#define CE_REG_FR_RIO_GAIN__A
#define CE_REG_FR_BYPASS__A
#define CE_REG_FR_PM_SET__A
#define CE_REG_FR_ERR_SH__A
#define CE_REG_FR_MAN_SH__A
#define CE_REG_FR_TAP_SH__A
#define EQ_COMM_EXEC__A
#define EQ_REG_COMM_EXEC__A
#define EQ_REG_COMM_MB__A
#define EQ_REG_IS_GAIN_MAN__A
#define EQ_REG_IS_GAIN_EXP__A
#define EQ_REG_IS_CLIP_EXP__A
#define EQ_REG_SN_CEGAIN__A
#define EQ_REG_SN_OFFSET__A
#define EQ_REG_RC_SEL_CAR__A
#define EQ_REG_RC_SEL_CAR_INIT
#define EQ_REG_RC_SEL_CAR_DIV_ON
#define EQ_REG_RC_SEL_CAR_PASS_A_CC
#define EQ_REG_RC_SEL_CAR_PASS_B_CE
#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC
#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE
#define EQ_REG_RC_SEL_CAR_MEAS_A_CC
#define EQ_REG_RC_SEL_CAR_MEAS_B_CE
#define EQ_REG_OT_CONST__A
#define EQ_REG_OT_ALPHA__A
#define EQ_REG_OT_QNT_THRES0__A
#define EQ_REG_OT_QNT_THRES1__A
#define EQ_REG_OT_CSI_STEP__A
#define EQ_REG_OT_CSI_OFFSET__A
#define EQ_REG_TD_REQ_SMB_CNT__A
#define EQ_REG_TD_TPS_PWR_OFS__A
#define EC_SB_REG_COMM_EXEC__A
#define EC_SB_REG_TR_MODE__A
#define EC_SB_REG_TR_MODE_8K
#define EC_SB_REG_TR_MODE_2K
#define EC_SB_REG_CONST__A
#define EC_SB_REG_CONST_QPSK
#define EC_SB_REG_CONST_16QAM
#define EC_SB_REG_CONST_64QAM
#define EC_SB_REG_ALPHA__A
#define EC_SB_REG_PRIOR__A
#define EC_SB_REG_PRIOR_HI
#define EC_SB_REG_PRIOR_LO
#define EC_SB_REG_CSI_HI__A
#define EC_SB_REG_CSI_LO__A
#define EC_SB_REG_SMB_TGL__A
#define EC_SB_REG_SNR_HI__A
#define EC_SB_REG_SNR_MID__A
#define EC_SB_REG_SNR_LO__A
#define EC_SB_REG_SCALE_MSB__A
#define EC_SB_REG_SCALE_BIT2__A
#define EC_SB_REG_SCALE_LSB__A
#define EC_SB_REG_CSI_OFS__A
#define EC_VD_REG_COMM_EXEC__A
#define EC_VD_REG_FORCE__A
#define EC_VD_REG_SET_CODERATE__A
#define EC_VD_REG_SET_CODERATE_C1_2
#define EC_VD_REG_SET_CODERATE_C2_3
#define EC_VD_REG_SET_CODERATE_C3_4
#define EC_VD_REG_SET_CODERATE_C5_6
#define EC_VD_REG_SET_CODERATE_C7_8
#define EC_VD_REG_REQ_SMB_CNT__A
#define EC_VD_REG_RLK_ENA__A
#define EC_OD_REG_COMM_EXEC__A
#define EC_OD_REG_SYNC__A
#define EC_OD_DEINT_RAM__A
#define EC_RS_REG_COMM_EXEC__A
#define EC_RS_REG_REQ_PCK_CNT__A
#define EC_RS_REG_VAL__A
#define EC_RS_REG_VAL_PCK
#define EC_RS_EC_RAM__A
#define EC_OC_REG_COMM_EXEC__A
#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE
#define EC_OC_REG_COMM_EXEC_CTL_HOLD
#define EC_OC_REG_COMM_INT_STA__A
#define EC_OC_REG_OC_MODE_LOP__A
#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M
#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE
#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE
#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M
#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC
#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M
#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL
#define EC_OC_REG_OC_MODE_HIP__A
#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR
#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M
#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE
#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE
#define EC_OC_REG_OC_MPG_SIO__A
#define EC_OC_REG_OC_MPG_SIO__M
#define EC_OC_REG_OC_MON_SIO__A
#define EC_OC_REG_DTO_INC_LOP__A
#define EC_OC_REG_DTO_INC_HIP__A
#define EC_OC_REG_SNC_ISC_LVL__A
#define EC_OC_REG_SNC_ISC_LVL_OSC__M
#define EC_OC_REG_TMD_TOP_MODE__A
#define EC_OC_REG_TMD_TOP_CNT__A
#define EC_OC_REG_TMD_HIL_MAR__A
#define EC_OC_REG_TMD_LOL_MAR__A
#define EC_OC_REG_TMD_CUR_CNT__A
#define EC_OC_REG_AVR_ASH_CNT__A
#define EC_OC_REG_AVR_BSH_CNT__A
#define EC_OC_REG_RCN_MODE__A
#define EC_OC_REG_RCN_CRA_LOP__A
#define EC_OC_REG_RCN_CRA_HIP__A
#define EC_OC_REG_RCN_CST_LOP__A
#define EC_OC_REG_RCN_CST_HIP__A
#define EC_OC_REG_RCN_SET_LVL__A
#define EC_OC_REG_RCN_GAI_LVL__A
#define EC_OC_REG_RCN_CLP_LOP__A
#define EC_OC_REG_RCN_CLP_HIP__A
#define EC_OC_REG_RCN_MAP_LOP__A
#define EC_OC_REG_RCN_MAP_HIP__A
#define EC_OC_REG_OCR_MPG_UOS__A
#define EC_OC_REG_OCR_MPG_UOS__M
#define EC_OC_REG_OCR_MPG_UOS_INIT
#define EC_OC_REG_OCR_MPG_USR_DAT__A
#define EC_OC_REG_OCR_MON_UOS__A
#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE
#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE
#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE
#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE
#define EC_OC_REG_OCR_MON_WRI__A
#define EC_OC_REG_OCR_MON_WRI_INIT
#define EC_OC_REG_IPR_INV_MPG__A
#define CC_REG_OSC_MODE__A
#define CC_REG_OSC_MODE_M20
#define CC_REG_PLL_MODE__A
#define CC_REG_PLL_MODE_BYPASS_PLL
#define CC_REG_PLL_MODE_PUMP_CUR_12
#define CC_REG_REF_DIVIDE__A
#define CC_REG_PWD_MODE__A
#define CC_REG_PWD_MODE_DOWN_PLL
#define CC_REG_UPDATE__A
#define CC_REG_UPDATE_KEY
#define CC_REG_JTAGID_L__A
#define LC_COMM_EXEC__A
#define LC_RA_RAM_IFINCR_NOM_L__A
#define LC_RA_RAM_FILTER_SYM_SET__A
#define LC_RA_RAM_FILTER_SYM_SET__PRE
#define LC_RA_RAM_FILTER_CRMM_A__A
#define LC_RA_RAM_FILTER_CRMM_A__PRE
#define LC_RA_RAM_FILTER_CRMM_B__A
#define LC_RA_RAM_FILTER_CRMM_B__PRE
#define LC_RA_RAM_FILTER_SRMM_A__A
#define LC_RA_RAM_FILTER_SRMM_A__PRE
#define LC_RA_RAM_FILTER_SRMM_B__A
#define LC_RA_RAM_FILTER_SRMM_B__PRE
#define B_HI_COMM_EXEC__A
#define B_HI_COMM_MB__A
#define B_HI_CT_REG_COMM_STATE__A
#define B_HI_RA_RAM_SRV_RES__A
#define B_HI_RA_RAM_SRV_CMD__A
#define B_HI_RA_RAM_SRV_CMD_RESET
#define B_HI_RA_RAM_SRV_CMD_CONFIG
#define B_HI_RA_RAM_SRV_CMD_EXECUTE
#define B_HI_RA_RAM_SRV_RST_KEY__A
#define B_HI_RA_RAM_SRV_RST_KEY_ACT
#define B_HI_RA_RAM_SRV_CFG_KEY__A
#define B_HI_RA_RAM_SRV_CFG_DIV__A
#define B_HI_RA_RAM_SRV_CFG_BDL__A
#define B_HI_RA_RAM_SRV_CFG_WUP__A
#define B_HI_RA_RAM_SRV_CFG_ACT__A
#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON
#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M
#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF
#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON
#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE
#define B_HI_RA_RAM_USR_BEGIN__A
#define B_HI_IF_RAM_TRP_BPT0__AX
#define B_HI_IF_RAM_USR_BEGIN__A
#define B_SC_COMM_EXEC__A
#define B_SC_COMM_EXEC_CTL_STOP
#define B_SC_COMM_STATE__A
#define B_SC_RA_RAM_PARAM0__A
#define B_SC_RA_RAM_PARAM1__A
#define B_SC_RA_RAM_CMD_ADDR__A
#define B_SC_RA_RAM_CMD__A
#define B_SC_RA_RAM_CMD_PROC_START
#define B_SC_RA_RAM_CMD_SET_PREF_PARAM
#define B_SC_RA_RAM_CMD_GET_OP_PARAM
#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M
#define B_SC_RA_RAM_LOCKTRACK_MIN
#define B_SC_RA_RAM_OP_PARAM_MODE_2K
#define B_SC_RA_RAM_OP_PARAM_MODE_8K
#define B_SC_RA_RAM_OP_PARAM_GUARD_32
#define B_SC_RA_RAM_OP_PARAM_GUARD_16
#define B_SC_RA_RAM_OP_PARAM_GUARD_8
#define B_SC_RA_RAM_OP_PARAM_GUARD_4
#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK
#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16
#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64
#define B_SC_RA_RAM_OP_PARAM_HIER_NO
#define B_SC_RA_RAM_OP_PARAM_HIER_A1
#define B_SC_RA_RAM_OP_PARAM_HIER_A2
#define B_SC_RA_RAM_OP_PARAM_HIER_A4
#define B_SC_RA_RAM_OP_PARAM_RATE_1_2
#define B_SC_RA_RAM_OP_PARAM_RATE_2_3
#define B_SC_RA_RAM_OP_PARAM_RATE_3_4
#define B_SC_RA_RAM_OP_PARAM_RATE_5_6
#define B_SC_RA_RAM_OP_PARAM_RATE_7_8
#define B_SC_RA_RAM_OP_PARAM_PRIO_HI
#define B_SC_RA_RAM_OP_PARAM_PRIO_LO
#define B_SC_RA_RAM_OP_AUTO_MODE__M
#define B_SC_RA_RAM_OP_AUTO_GUARD__M
#define B_SC_RA_RAM_OP_AUTO_CONST__M
#define B_SC_RA_RAM_OP_AUTO_HIER__M
#define B_SC_RA_RAM_OP_AUTO_RATE__M
#define B_SC_RA_RAM_LOCK__A
#define B_SC_RA_RAM_LOCK_DEMOD__M
#define B_SC_RA_RAM_LOCK_FEC__M
#define B_SC_RA_RAM_LOCK_MPEG__M
#define B_SC_RA_RAM_BE_OPT_ENA__A
#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT
#define B_SC_RA_RAM_BE_OPT_DELAY__A
#define B_SC_RA_RAM_CONFIG__A
#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M
#define B_SC_RA_RAM_CONFIG_FREQSCAN__M
#define B_SC_RA_RAM_CONFIG_SLAVE__M
#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M
#define B_SC_RA_RAM_CO_TD_CAL_2K__A
#define B_SC_RA_RAM_CO_TD_CAL_8K__A
#define B_SC_RA_RAM_IF_SAVE__AX
#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A
#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A
#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A
#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A
#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A
#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A
#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A
#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A
#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A
#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE
#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A
#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE
#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A
#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE
#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A
#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE
#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A
#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE
#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A
#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE
#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A
#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE
#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A
#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE
#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A
#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE
#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A
#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE
#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A
#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE
#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A
#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE
#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A
#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A
#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A
#define B_SC_RA_RAM_BAND__A
#define B_SC_RA_RAM_LC_ABS_2K__A
#define B_SC_RA_RAM_LC_ABS_2K__PRE
#define B_SC_RA_RAM_LC_ABS_8K__A
#define B_SC_RA_RAM_LC_ABS_8K__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE
#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE
#define B_SC_RA_RAM_DRIVER_VERSION__AX
#define B_SC_RA_RAM_PROC_LOCKTRACK
#define B_FE_COMM_EXEC__A
#define B_FE_AD_REG_COMM_EXEC__A
#define B_FE_AD_REG_FDB_IN__A
#define B_FE_AD_REG_PD__A
#define B_FE_AD_REG_INVEXT__A
#define B_FE_AD_REG_CLKNEG__A
#define B_FE_AG_REG_COMM_EXEC__A
#define B_FE_AG_REG_AG_MODE_LOP__A
#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M
#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC
#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC
#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M
#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M
#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC
#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC
#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M
#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC
#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC
#define B_FE_AG_REG_AG_MODE_HIP__A
#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M
#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC
#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC
#define B_FE_AG_REG_AG_PGA_MODE__A
#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN
#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
#define B_FE_AG_REG_AG_AGC_SIO__A
#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT
#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT
#define B_FE_AG_REG_AG_PWD__A
#define B_FE_AG_REG_AG_PWD_PWD_PD2__M
#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE
#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE
#define B_FE_AG_REG_DCE_AUR_CNT__A
#define B_FE_AG_REG_DCE_RUR_CNT__A
#define B_FE_AG_REG_ACE_AUR_CNT__A
#define B_FE_AG_REG_ACE_RUR_CNT__A
#define B_FE_AG_REG_CDR_RUR_CNT__A
#define B_FE_AG_REG_EGC_RUR_CNT__A
#define B_FE_AG_REG_EGC_SET_LVL__A
#define B_FE_AG_REG_EGC_SET_LVL__M
#define B_FE_AG_REG_EGC_FLA_RGN__A
#define B_FE_AG_REG_EGC_SLO_RGN__A
#define B_FE_AG_REG_EGC_JMP_PSN__A
#define B_FE_AG_REG_EGC_FLA_INC__A
#define B_FE_AG_REG_EGC_FLA_DEC__A
#define B_FE_AG_REG_EGC_SLO_INC__A
#define B_FE_AG_REG_EGC_SLO_DEC__A
#define B_FE_AG_REG_EGC_FAS_INC__A
#define B_FE_AG_REG_EGC_FAS_DEC__A
#define B_FE_AG_REG_PM1_AGC_WRI__A
#define B_FE_AG_REG_PM1_AGC_WRI__M
#define B_FE_AG_REG_GC1_AGC_RIC__A
#define B_FE_AG_REG_GC1_AGC_OFF__A
#define B_FE_AG_REG_GC1_AGC_MAX__A
#define B_FE_AG_REG_GC1_AGC_MIN__A
#define B_FE_AG_REG_GC1_AGC_DAT__A
#define B_FE_AG_REG_GC1_AGC_DAT__M
#define B_FE_AG_REG_PM2_AGC_WRI__A
#define B_FE_AG_REG_IND_WIN__A
#define B_FE_AG_REG_IND_THD_LOL__A
#define B_FE_AG_REG_IND_THD_HIL__A
#define B_FE_AG_REG_IND_DEL__A
#define B_FE_AG_REG_IND_PD1_WRI__A
#define B_FE_AG_REG_PDA_AUR_CNT__A
#define B_FE_AG_REG_PDA_RUR_CNT__A
#define B_FE_AG_REG_PDA_AVE_DAT__A
#define B_FE_AG_REG_PDC_RUR_CNT__A
#define B_FE_AG_REG_PDC_SET_LVL__A
#define B_FE_AG_REG_PDC_FLA_RGN__A
#define B_FE_AG_REG_PDC_JMP_PSN__A
#define B_FE_AG_REG_PDC_FLA_STP__A
#define B_FE_AG_REG_PDC_SLO_STP__A
#define B_FE_AG_REG_PDC_PD2_WRI__A
#define B_FE_AG_REG_PDC_MAP_DAT__A
#define B_FE_AG_REG_PDC_MAX__A
#define B_FE_AG_REG_TGA_AUR_CNT__A
#define B_FE_AG_REG_TGA_RUR_CNT__A
#define B_FE_AG_REG_TGA_AVE_DAT__A
#define B_FE_AG_REG_TGC_RUR_CNT__A
#define B_FE_AG_REG_TGC_SET_LVL__A
#define B_FE_AG_REG_TGC_SET_LVL__M
#define B_FE_AG_REG_TGC_FLA_RGN__A
#define B_FE_AG_REG_TGC_JMP_PSN__A
#define B_FE_AG_REG_TGC_FLA_STP__A
#define B_FE_AG_REG_TGC_SLO_STP__A
#define B_FE_AG_REG_TGC_MAP_DAT__A
#define B_FE_AG_REG_FGM_WRI__A
#define B_FE_AG_REG_BGC_FGC_WRI__A
#define B_FE_AG_REG_BGC_CGC_WRI__A
#define B_FE_FS_REG_COMM_EXEC__A
#define B_FE_FS_REG_ADD_INC_LOP__A
#define B_FE_FD_REG_COMM_EXEC__A
#define B_FE_FD_REG_SCL__A
#define B_FE_FD_REG_MAX_LEV__A
#define B_FE_FD_REG_NR__A
#define B_FE_FD_REG_MEAS_VAL__A
#define B_FE_IF_REG_COMM_EXEC__A
#define B_FE_IF_REG_INCR0__A
#define B_FE_IF_REG_INCR0__W
#define B_FE_IF_REG_INCR0__M
#define B_FE_IF_REG_INCR1__A
#define B_FE_IF_REG_INCR1__M
#define B_FE_CF_REG_COMM_EXEC__A
#define B_FE_CF_REG_SCL__A
#define B_FE_CF_REG_MAX_LEV__A
#define B_FE_CF_REG_NR__A
#define B_FE_CF_REG_IMP_VAL__A
#define B_FE_CF_REG_MEAS_VAL__A
#define B_FE_CU_REG_COMM_EXEC__A
#define B_FE_CU_REG_FRM_CNT_RST__A
#define B_FE_CU_REG_FRM_CNT_STR__A
#define B_FE_CU_REG_CTR_NFC_ICR__A
#define B_FE_CU_REG_CTR_NFC_OCR__A
#define B_FE_CU_REG_DIV_NFC_CLP__A
#define B_FT_COMM_EXEC__A
#define B_FT_REG_COMM_EXEC__A
#define B_CP_COMM_EXEC__A
#define B_CP_REG_COMM_EXEC__A
#define B_CP_REG_INTERVAL__A
#define B_CP_REG_BR_SPL_OFFSET__A
#define B_CP_REG_BR_STR_DEL__A
#define B_CP_REG_RT_ANG_INC0__A
#define B_CP_REG_RT_ANG_INC1__A
#define B_CP_REG_RT_DETECT_TRH__A
#define B_CP_REG_AC_NEXP_OFFS__A
#define B_CP_REG_AC_AVER_POW__A
#define B_CP_REG_AC_MAX_POW__A
#define B_CP_REG_AC_WEIGHT_MAN__A
#define B_CP_REG_AC_WEIGHT_EXP__A
#define B_CP_REG_AC_AMP_MODE__A
#define B_CP_REG_AC_AMP_FIX__A
#define B_CP_REG_AC_ANG_MODE__A
#define B_CE_COMM_EXEC__A
#define B_CE_REG_COMM_EXEC__A
#define B_CE_REG_TAPSET__A
#define B_CE_REG_AVG_POW__A
#define B_CE_REG_MAX_POW__A
#define B_CE_REG_ATT__A
#define B_CE_REG_NRED__A
#define B_CE_REG_NE_ERR_SELECT__A
#define B_CE_REG_NE_TD_CAL__A
#define B_CE_REG_NE_MIXAVG__A
#define B_CE_REG_NE_NUPD_OFS__A
#define B_CE_REG_PE_NEXP_OFFS__A
#define B_CE_REG_PE_TIMESHIFT__A
#define B_CE_REG_TP_A0_TAP_NEW__A
#define B_CE_REG_TP_A0_TAP_NEW_VALID__A
#define B_CE_REG_TP_A0_MU_LMS_STEP__A
#define B_CE_REG_TP_A1_TAP_NEW__A
#define B_CE_REG_TP_A1_TAP_NEW_VALID__A
#define B_CE_REG_TP_A1_MU_LMS_STEP__A
#define B_CE_REG_TI_PHN_ENABLE__A
#define B_CE_REG_FI_SHT_INCR__A
#define B_CE_REG_FI_EXP_NORM__A
#define B_CE_REG_IR_INPUTSEL__A
#define B_CE_REG_IR_STARTPOS__A
#define B_CE_REG_IR_NEXP_THRES__A
#define B_CE_REG_FR_TREAL00__A
#define B_CE_REG_FR_TIMAG00__A
#define B_CE_REG_FR_TREAL01__A
#define B_CE_REG_FR_TIMAG01__A
#define B_CE_REG_FR_TREAL02__A
#define B_CE_REG_FR_TIMAG02__A
#define B_CE_REG_FR_TREAL03__A
#define B_CE_REG_FR_TIMAG03__A
#define B_CE_REG_FR_TREAL04__A
#define B_CE_REG_FR_TIMAG04__A
#define B_CE_REG_FR_TREAL05__A
#define B_CE_REG_FR_TIMAG05__A
#define B_CE_REG_FR_TREAL06__A
#define B_CE_REG_FR_TIMAG06__A
#define B_CE_REG_FR_TREAL07__A
#define B_CE_REG_FR_TIMAG07__A
#define B_CE_REG_FR_TREAL08__A
#define B_CE_REG_FR_TIMAG08__A
#define B_CE_REG_FR_TREAL09__A
#define B_CE_REG_FR_TIMAG09__A
#define B_CE_REG_FR_TREAL10__A
#define B_CE_REG_FR_TIMAG10__A
#define B_CE_REG_FR_TREAL11__A
#define B_CE_REG_FR_TIMAG11__A
#define B_CE_REG_FR_MID_TAP__A
#define B_CE_REG_FR_SQS_G00__A
#define B_CE_REG_FR_SQS_G01__A
#define B_CE_REG_FR_SQS_G02__A
#define B_CE_REG_FR_SQS_G03__A
#define B_CE_REG_FR_SQS_G04__A
#define B_CE_REG_FR_SQS_G05__A
#define B_CE_REG_FR_SQS_G06__A
#define B_CE_REG_FR_SQS_G07__A
#define B_CE_REG_FR_SQS_G08__A
#define B_CE_REG_FR_SQS_G09__A
#define B_CE_REG_FR_SQS_G10__A
#define B_CE_REG_FR_SQS_G11__A
#define B_CE_REG_FR_SQS_G12__A
#define B_CE_REG_FR_RIO_G00__A
#define B_CE_REG_FR_RIO_G01__A
#define B_CE_REG_FR_RIO_G02__A
#define B_CE_REG_FR_RIO_G03__A
#define B_CE_REG_FR_RIO_G04__A
#define B_CE_REG_FR_RIO_G05__A
#define B_CE_REG_FR_RIO_G06__A
#define B_CE_REG_FR_RIO_G07__A
#define B_CE_REG_FR_RIO_G08__A
#define B_CE_REG_FR_RIO_G09__A
#define B_CE_REG_FR_RIO_G10__A
#define B_CE_REG_FR_MODE__A
#define B_CE_REG_FR_SQS_TRH__A
#define B_CE_REG_FR_RIO_GAIN__A
#define B_CE_REG_FR_BYPASS__A
#define B_CE_REG_FR_PM_SET__A
#define B_CE_REG_FR_ERR_SH__A
#define B_CE_REG_FR_MAN_SH__A
#define B_CE_REG_FR_TAP_SH__A
#define B_EQ_COMM_EXEC__A
#define B_EQ_REG_COMM_EXEC__A
#define B_EQ_REG_COMM_MB__A
#define B_EQ_REG_IS_GAIN_MAN__A
#define B_EQ_REG_IS_GAIN_EXP__A
#define B_EQ_REG_IS_CLIP_EXP__A
#define B_EQ_REG_SN_CEGAIN__A
#define B_EQ_REG_SN_OFFSET__A
#define B_EQ_REG_RC_SEL_CAR__A
#define B_EQ_REG_RC_SEL_CAR_INIT
#define B_EQ_REG_RC_SEL_CAR_DIV_ON
#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC
#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE
#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC
#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE
#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC
#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE
#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M
#define B_EQ_REG_OT_CONST__A
#define B_EQ_REG_OT_ALPHA__A
#define B_EQ_REG_OT_QNT_THRES0__A
#define B_EQ_REG_OT_QNT_THRES1__A
#define B_EQ_REG_OT_CSI_STEP__A
#define B_EQ_REG_OT_CSI_OFFSET__A
#define B_EQ_REG_TD_REQ_SMB_CNT__A
#define B_EQ_REG_TD_TPS_PWR_OFS__A
#define B_EC_SB_REG_COMM_EXEC__A
#define B_EC_SB_REG_TR_MODE__A
#define B_EC_SB_REG_TR_MODE_8K
#define B_EC_SB_REG_TR_MODE_2K
#define B_EC_SB_REG_CONST__A
#define B_EC_SB_REG_CONST_QPSK
#define B_EC_SB_REG_CONST_16QAM
#define B_EC_SB_REG_CONST_64QAM
#define B_EC_SB_REG_ALPHA__A
#define B_EC_SB_REG_PRIOR__A
#define B_EC_SB_REG_PRIOR_HI
#define B_EC_SB_REG_PRIOR_LO
#define B_EC_SB_REG_CSI_HI__A
#define B_EC_SB_REG_CSI_LO__A
#define B_EC_SB_REG_SMB_TGL__A
#define B_EC_SB_REG_SNR_HI__A
#define B_EC_SB_REG_SNR_MID__A
#define B_EC_SB_REG_SNR_LO__A
#define B_EC_SB_REG_SCALE_MSB__A
#define B_EC_SB_REG_SCALE_BIT2__A
#define B_EC_SB_REG_SCALE_LSB__A
#define B_EC_SB_REG_CSI_OFS0__A
#define B_EC_SB_REG_CSI_OFS1__A
#define B_EC_SB_REG_CSI_OFS2__A
#define B_EC_VD_REG_COMM_EXEC__A
#define B_EC_VD_REG_FORCE__A
#define B_EC_VD_REG_SET_CODERATE__A
#define B_EC_VD_REG_SET_CODERATE_C1_2
#define B_EC_VD_REG_SET_CODERATE_C2_3
#define B_EC_VD_REG_SET_CODERATE_C3_4
#define B_EC_VD_REG_SET_CODERATE_C5_6
#define B_EC_VD_REG_SET_CODERATE_C7_8
#define B_EC_VD_REG_REQ_SMB_CNT__A
#define B_EC_VD_REG_RLK_ENA__A
#define B_EC_OD_REG_COMM_EXEC__A
#define B_EC_OD_REG_SYNC__A
#define B_EC_OD_DEINT_RAM__A
#define B_EC_RS_REG_COMM_EXEC__A
#define B_EC_RS_REG_REQ_PCK_CNT__A
#define B_EC_RS_REG_VAL__A
#define B_EC_RS_REG_VAL_PCK
#define B_EC_RS_EC_RAM__A
#define B_EC_OC_REG_COMM_EXEC__A
#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE
#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD
#define B_EC_OC_REG_COMM_INT_STA__A
#define B_EC_OC_REG_OC_MODE_LOP__A
#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M
#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE
#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE
#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M
#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC
#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M
#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL
#define B_EC_OC_REG_OC_MODE_HIP__A
#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR
#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M
#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE
#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE
#define B_EC_OC_REG_OC_MPG_SIO__A
#define B_EC_OC_REG_OC_MPG_SIO__M
#define B_EC_OC_REG_DTO_INC_LOP__A
#define B_EC_OC_REG_DTO_INC_HIP__A
#define B_EC_OC_REG_SNC_ISC_LVL__A
#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M
#define B_EC_OC_REG_TMD_TOP_MODE__A
#define B_EC_OC_REG_TMD_TOP_CNT__A
#define B_EC_OC_REG_TMD_HIL_MAR__A
#define B_EC_OC_REG_TMD_LOL_MAR__A
#define B_EC_OC_REG_TMD_CUR_CNT__A
#define B_EC_OC_REG_AVR_ASH_CNT__A
#define B_EC_OC_REG_AVR_BSH_CNT__A
#define B_EC_OC_REG_RCN_MODE__A
#define B_EC_OC_REG_RCN_CRA_LOP__A
#define B_EC_OC_REG_RCN_CRA_HIP__A
#define B_EC_OC_REG_RCN_CST_LOP__A
#define B_EC_OC_REG_RCN_CST_HIP__A
#define B_EC_OC_REG_RCN_SET_LVL__A
#define B_EC_OC_REG_RCN_GAI_LVL__A
#define B_EC_OC_REG_RCN_CLP_LOP__A
#define B_EC_OC_REG_RCN_CLP_HIP__A
#define B_EC_OC_REG_RCN_MAP_LOP__A
#define B_EC_OC_REG_RCN_MAP_HIP__A
#define B_EC_OC_REG_OCR_MPG_UOS__A
#define B_EC_OC_REG_OCR_MPG_UOS__M
#define B_EC_OC_REG_OCR_MPG_UOS_INIT
#define B_EC_OC_REG_OCR_MPG_USR_DAT__A
#define B_EC_OC_REG_IPR_INV_MPG__A
#define B_EC_OC_REG_DTO_CLKMODE__A
#define B_EC_OC_REG_DTO_PER__A
#define B_EC_OC_REG_DTO_BUR__A
#define B_EC_OC_REG_RCR_CLKMODE__A
#define B_CC_REG_OSC_MODE__A
#define B_CC_REG_OSC_MODE_M20
#define B_CC_REG_PLL_MODE__A
#define B_CC_REG_PLL_MODE_BYPASS_PLL
#define B_CC_REG_PLL_MODE_PUMP_CUR_12
#define B_CC_REG_REF_DIVIDE__A
#define B_CC_REG_PWD_MODE__A
#define B_CC_REG_PWD_MODE_DOWN_PLL
#define B_CC_REG_UPDATE__A
#define B_CC_REG_UPDATE_KEY
#define B_CC_REG_JTAGID_L__A
#define B_CC_REG_DIVERSITY__A
#define B_LC_COMM_EXEC__A
#define B_LC_RA_RAM_IFINCR_NOM_L__A
#define B_LC_RA_RAM_FILTER_SYM_SET__A
#define B_LC_RA_RAM_FILTER_SYM_SET__PRE
#define B_LC_RA_RAM_FILTER_CRMM_A__A
#define B_LC_RA_RAM_FILTER_CRMM_A__PRE
#define B_LC_RA_RAM_FILTER_CRMM_B__A
#define B_LC_RA_RAM_FILTER_CRMM_B__PRE
#define B_LC_RA_RAM_FILTER_SRMM_A__A
#define B_LC_RA_RAM_FILTER_SRMM_A__PRE
#define B_LC_RA_RAM_FILTER_SRMM_B__A
#define B_LC_RA_RAM_FILTER_SRMM_B__PRE

#endif