drxd_firm.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0-only
/*
 * drxd_firm.c : DRXD firmware tables
 *
 * Copyright (C) 2006-2007 Micronas
 */

/* TODO: generate this file with a script from a settings file */

/* Contains A2 firmware version: 1.4.2
 * Contains B1 firmware version: 3.3.33
 * Contains settings from driver 1.4.23
*/

#include "drxd_firm.h"

#define ADDRESS(x) …
#define LENGTH(x) …

/* Is written via block write, must be little endian */
#define DATA16(x) …

#define WRBLOCK(a, l) …
#define WR16(a, d) …

#define END_OF_TABLE …

/* HI firmware patches */

#define HI_TR_FUNC_ADDR …
#define HI_TR_FUNC_SIZE …

u8 DRXD_InitAtomicRead[] = …;

/* Pins D0 and D1 of the parallel MPEG output can be used
   to set the I2C address of a device. */

#define HI_RST_FUNC_ADDR …
#define HI_RST_FUNC_SIZE …

/* D0 Version */
u8 DRXD_HiI2cPatch_1[] = …;

/* D0,D1 Version */
u8 DRXD_HiI2cPatch_3[] = …;

u8 DRXD_ResetCEFR[] = …;

u8 DRXD_InitFEA2_1[] = …;

   /* with PGA */
/*   WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A   , 0x0004), */
   /* without PGA */
/*   WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A   , 0x0001), */
/*   WR16(FE_AG_REG_AG_AGC_SIO__A,  (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
/*   WR16(FE_AG_REG_AG_PWD__A        ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/

u8 DRXD_InitFEA2_2[] = …;

u8 DRXD_InitFEB1_1[] = …;

	/* with PGA */
/*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   , 0x0000, 0x0000); */
       /* without PGA */
/*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   ,
	     B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
									     /*   WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
/*   WR16(B_FE_AG_REG_AG_PWD__A    ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/

u8 DRXD_InitFEB1_2[] = …;

u8 DRXD_InitCPA2[] = …;

u8 DRXD_InitCPB1[] = …;

u8 DRXD_InitCEA2[] = …;

u8 DRXD_InitCEB1[] = …;

u8 DRXD_InitEQA2[] = …;

u8 DRXD_InitEQB1[] = …;

u8 DRXD_ResetECRAM[] = …;

u8 DRXD_InitECA2[] = …;

u8 DRXD_InitECB1[] = …;

u8 DRXD_ResetECA2[] = …;

u8 DRXD_InitSC[] = …;

/* Diversity settings */

u8 DRXD_InitDiversityFront[] = …;

u8 DRXD_InitDiversityEnd[] = …;

u8 DRXD_DisableDiversity[] = …;

u8 DRXD_StartDiversityFront[] = …;

u8 DRXD_StartDiversityEnd[] = …;

u8 DRXD_DiversityDelay8MHZ[] = …;

u8 DRXD_DiversityDelay6MHZ[] = …/* also used ok for 7 MHz */
{ … };
linux/drivers/media/dvb-frontends/drxd_firm.c
