/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved * * This program may alternatively be licensed under a proprietary license from * MaxLinear, Inc. * */ #ifndef __MXL58X_REGISTERS_H__ #define __MXL58X_REGISTERS_H__ #define HYDRA_INTR_STATUS_REG … #define HYDRA_INTR_MASK_REG … #define HYDRA_CRYSTAL_SETTING … #define HYDRA_CRYSTAL_CAP … #define HYDRA_CPU_RESET_REG … #define HYDRA_CPU_RESET_DATA … #define HYDRA_RESET_TRANSPORT_FIFO_REG … #define HYDRA_RESET_TRANSPORT_FIFO_DATA … #define HYDRA_RESET_BBAND_REG … #define HYDRA_RESET_BBAND_DATA … #define HYDRA_RESET_XBAR_REG … #define HYDRA_RESET_XBAR_DATA … #define HYDRA_MODULES_CLK_1_REG … #define HYDRA_DISABLE_CLK_1 … #define HYDRA_MODULES_CLK_2_REG … #define HYDRA_DISABLE_CLK_2 … #define HYDRA_PRCM_ROOT_CLK_REG … #define HYDRA_PRCM_ROOT_CLK_DISABLE … #define HYDRA_CPU_RESET_CHECK_REG … #define HYDRA_CPU_RESET_CHECK_OFFSET … #define HYDRA_SKU_ID_REG … #define FW_DL_SIGN_ADDR … /* Register to check if FW is running or not */ #define HYDRA_HEAR_BEAT … /* Firmware version */ #define HYDRA_FIRMWARE_VERSION … #define HYDRA_FW_RC_VERSION … /* Firmware patch version */ #define HYDRA_FIRMWARE_PATCH_VERSION … /* SOC operating temperature in C */ #define HYDRA_TEMPARATURE … /* Demod & Tuner status registers */ /* Demod 0 status base address */ #define HYDRA_DEMOD_0_BASE_ADDR … /* Tuner 0 status base address */ #define HYDRA_TUNER_0_BASE_ADDR … #define POWER_FROM_ADCRSSI_READBACK … /* Macros to determine base address of respective demod or tuner */ #define HYDRA_DMD_STATUS_OFFSET(demodID) … #define HYDRA_TUNER_STATUS_OFFSET(tunerID) … /* Demod status address offset from respective demod's base address */ #define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET … #define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET … #define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET … #define HYDRA_DMD_STANDARD_ADDR_OFFSET … #define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET … #define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET … #define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET … #define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET … #define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET … #define HYDRA_DMD_SNR_ADDR_OFFSET … #define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET … #define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET … #define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET … #define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET … #define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET … #define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET … #define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET … #define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET … #define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET … #define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET … #define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET … #define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET … #define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET … #define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET … #define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET … /* Debug-purpose DVB-S DMD 0 */ #define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET … #define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET … #define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET … #define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET … #define HYDRA_DMD_TUNER_ID_ADDR_OFFSET … #define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET … #define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET … #define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET … #define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR … #define HYDRA_DMD_STATUS_INPUT_POWER_ADDR … /* DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" */ #define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR … #define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR … #define DMD0_SPECTRUM_MIN_GAIN_STATUS … #define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE … #define DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE … #define HYDRA_DMD_STATUS_END_ADDR_OFFSET … /* Tuner status address offset from respective tuners's base address */ #define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET … #define HYDRA_TUNER_AGC_LOCK_OFFSET … #define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET … #define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET … #define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET … #define HYDRA_TUNER_ENABLE_COMPLETE … #define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) … #define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) … #define HYDRA_VERSION … #define HYDRA_DEMOD0_VERSION … #define HYDRA_DEMOD1_VERSION … #define HYDRA_DEMOD2_VERSION … #define HYDRA_DEMOD3_VERSION … #define HYDRA_DEMOD4_VERSION … #define HYDRA_DEMOD5_VERSION … #define HYDRA_DEMOD6_VERSION … #define HYDRA_DEMOD7_VERSION … #define HYDRA_HEAR_BEAT … #define HYDRA_SKU_MGMT … #define MXL_HYDRA_FPGA_A_ADDRESS … #define MXL_HYDRA_FPGA_B_ADDRESS … /* TS control base address */ #define HYDRA_TS_CTRL_BASE_ADDR … #define MPEG_MUX_MODE_SLICE0_REG … #define MPEG_MUX_MODE_SLICE1_REG … #define PID_BANK_SEL_SLICE0_REG … #define PID_BANK_SEL_SLICE1_REG … #define MPEG_CLK_GATED_REG … #define MPEG_CLK_ALWAYS_ON_REG … #define HYDRA_REGULAR_PID_BANK_A_REG … #define HYDRA_FIXED_PID_BANK_A_REG … #define HYDRA_REGULAR_PID_BANK_B_REG … #define HYDRA_FIXED_PID_BANK_B_REG … #define FIXED_PID_TBL_REG_ADDRESS_0 … #define FIXED_PID_TBL_REG_ADDRESS_1 … #define FIXED_PID_TBL_REG_ADDRESS_2 … #define FIXED_PID_TBL_REG_ADDRESS_3 … #define FIXED_PID_TBL_REG_ADDRESS_4 … #define FIXED_PID_TBL_REG_ADDRESS_5 … #define FIXED_PID_TBL_REG_ADDRESS_6 … #define FIXED_PID_TBL_REG_ADDRESS_7 … #define REGULAR_PID_TBL_REG_ADDRESS_0 … #define REGULAR_PID_TBL_REG_ADDRESS_1 … #define REGULAR_PID_TBL_REG_ADDRESS_2 … #define REGULAR_PID_TBL_REG_ADDRESS_3 … #define REGULAR_PID_TBL_REG_ADDRESS_4 … #define REGULAR_PID_TBL_REG_ADDRESS_5 … #define REGULAR_PID_TBL_REG_ADDRESS_6 … #define REGULAR_PID_TBL_REG_ADDRESS_7 … /***************************************************************************/ #define PAD_MUX_GPIO_00_SYNC_BASEADDR … #define PAD_MUX_UART_RX_C_PINMUX_BASEADDR … #define XPT_PACKET_GAP_MIN_BASEADDR … #define XPT_NCO_COUNT_BASEADDR … #define XPT_NCO_COUNT_BASEADDR1 … /* V2 DigRF status register */ #define XPT_PID_BASEADDR … #define XPT_PID_REMAP_BASEADDR … #define XPT_KNOWN_PID_BASEADDR … #define XPT_PID_BASEADDR1 … #define XPT_PID_REMAP_BASEADDR1 … #define XPT_KNOWN_PID_BASEADDR1 … #define XPT_BERT_LOCK_BASEADDR … #define XPT_BERT_BASEADDR … #define XPT_BERT_INVERT_BASEADDR … #define XPT_BERT_HEADER_BASEADDR … #define XPT_BERT_BASEADDR1 … #define XPT_BERT_BIT_COUNT0_BASEADDR … #define XPT_BERT_BIT_COUNT0_BASEADDR1 … #define XPT_BERT_BIT_COUNT1_BASEADDR … #define XPT_BERT_BIT_COUNT1_BASEADDR1 … #define XPT_BERT_BIT_COUNT2_BASEADDR … #define XPT_BERT_BIT_COUNT2_BASEADDR1 … #define XPT_BERT_BIT_COUNT3_BASEADDR … #define XPT_BERT_BIT_COUNT3_BASEADDR1 … #define XPT_BERT_BIT_COUNT4_BASEADDR … #define XPT_BERT_BIT_COUNT4_BASEADDR1 … #define XPT_BERT_BIT_COUNT5_BASEADDR … #define XPT_BERT_BIT_COUNT5_BASEADDR1 … #define XPT_BERT_BIT_COUNT6_BASEADDR … #define XPT_BERT_BIT_COUNT6_BASEADDR1 … #define XPT_BERT_BIT_COUNT7_BASEADDR … #define XPT_BERT_BIT_COUNT7_BASEADDR1 … #define XPT_BERT_ERR_COUNT0_BASEADDR … #define XPT_BERT_ERR_COUNT0_BASEADDR1 … #define XPT_BERT_ERR_COUNT1_BASEADDR … #define XPT_BERT_ERR_COUNT1_BASEADDR1 … #define XPT_BERT_ERR_COUNT2_BASEADDR … #define XPT_BERT_ERR_COUNT2_BASEADDR1 … #define XPT_BERT_ERR_COUNT3_BASEADDR … #define XPT_BERT_ERR_COUNT3_BASEADDR1 … #define XPT_BERT_ERR_COUNT4_BASEADDR … #define XPT_BERT_ERR_COUNT4_BASEADDR1 … #define XPT_BERT_ERR_COUNT5_BASEADDR … #define XPT_BERT_ERR_COUNT5_BASEADDR1 … #define XPT_BERT_ERR_COUNT6_BASEADDR … #define XPT_BERT_ERR_COUNT6_BASEADDR1 … #define XPT_BERT_ERR_COUNT7_BASEADDR … #define XPT_BERT_ERR_COUNT7_BASEADDR1 … #define XPT_BERT_ERROR_BASEADDR … #define XPT_BERT_ANALYZER_BASEADDR … #define XPT_BERT_ANALYZER_BASEADDR1 … #define XPT_BERT_ANALYZER_BASEADDR2 … #define XPT_BERT_ANALYZER_BASEADDR3 … #define XPT_BERT_ANALYZER_BASEADDR4 … #define XPT_BERT_ANALYZER_BASEADDR5 … #define XPT_BERT_ANALYZER_BASEADDR6 … #define XPT_BERT_ANALYZER_BASEADDR7 … #define XPT_BERT_ANALYZER_BASEADDR8 … #define XPT_BERT_ANALYZER_BASEADDR9 … #define XPT_DMD0_BASEADDR … /* V2 AGC Gain Freeze & step */ #define DBG_ENABLE_DISABLE_AGC … #define WB_DFE0_DFE_FB_RF1_BASEADDR … #define WB_DFE1_DFE_FB_RF1_BASEADDR … #define WB_DFE2_DFE_FB_RF1_BASEADDR … #define WB_DFE3_DFE_FB_RF1_BASEADDR … #define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR … #define AFE_REG_AFE_REG_SPARE_BASEADDR … #define AFE_REG_AFE_REG_SPARE_BASEADDR1 … #define AFE_REG_AFE_REG_SPARE_BASEADDR2 … #define AFE_REG_AFE_REG_SPARE_BASEADDR3 … #define WB_DFE0_DFE_FB_AGC_BASEADDR … #define WB_DFE1_DFE_FB_AGC_BASEADDR … #define WB_DFE2_DFE_FB_AGC_BASEADDR … #define WB_DFE3_DFE_FB_AGC_BASEADDR … #define WDT_WD_INT_BASEADDR … #define FSK_TX_FTM_BASEADDR … #define FSK_TX_FTM_TX_CNT_BASEADDR … #define AFE_REG_D2A_FSK_BIAS_BASEADDR … #define DMD_TEI_BASEADDR … #endif /* __MXL58X_REGISTERS_H__ */
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