// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2008-2009 MontaVista Software Inc. * Copyright (C) 2008-2009 Texas Instruments Inc * * Based on the LCD driver for TI Avalanche processors written by * Ajay Singh and Shalom Hai. */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/fb.h> #include <linux/dma-mapping.h> #include <linux/device.h> #include <linux/platform_device.h> #include <linux/uaccess.h> #include <linux/pm_runtime.h> #include <linux/interrupt.h> #include <linux/wait.h> #include <linux/clk.h> #include <linux/cpufreq.h> #include <linux/console.h> #include <linux/regulator/consumer.h> #include <linux/spinlock.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/lcm.h> #include <video/da8xx-fb.h> #include <asm/div64.h> #define DRIVER_NAME … #define LCD_VERSION_1 … #define LCD_VERSION_2 … /* LCD Status Register */ #define LCD_END_OF_FRAME1 … #define LCD_END_OF_FRAME0 … #define LCD_PL_LOAD_DONE … #define LCD_FIFO_UNDERFLOW … #define LCD_SYNC_LOST … #define LCD_FRAME_DONE … /* LCD DMA Control Register */ #define LCD_DMA_BURST_SIZE(x) … #define LCD_DMA_BURST_1 … #define LCD_DMA_BURST_2 … #define LCD_DMA_BURST_4 … #define LCD_DMA_BURST_8 … #define LCD_DMA_BURST_16 … #define LCD_V1_END_OF_FRAME_INT_ENA … #define LCD_V2_END_OF_FRAME0_INT_ENA … #define LCD_V2_END_OF_FRAME1_INT_ENA … #define LCD_DUAL_FRAME_BUFFER_ENABLE … /* LCD Control Register */ #define LCD_CLK_DIVISOR(x) … #define LCD_RASTER_MODE … /* LCD Raster Control Register */ #define LCD_PALETTE_LOAD_MODE(x) … #define PALETTE_AND_DATA … #define PALETTE_ONLY … #define DATA_ONLY … #define LCD_MONO_8BIT_MODE … #define LCD_RASTER_ORDER … #define LCD_TFT_MODE … #define LCD_V1_UNDERFLOW_INT_ENA … #define LCD_V2_UNDERFLOW_INT_ENA … #define LCD_V1_PL_INT_ENA … #define LCD_V2_PL_INT_ENA … #define LCD_MONOCHROME_MODE … #define LCD_RASTER_ENABLE … #define LCD_TFT_ALT_ENABLE … #define LCD_STN_565_ENABLE … #define LCD_V2_DMA_CLK_EN … #define LCD_V2_LIDD_CLK_EN … #define LCD_V2_CORE_CLK_EN … #define LCD_V2_LPP_B10 … #define LCD_V2_TFT_24BPP_MODE … #define LCD_V2_TFT_24BPP_UNPACK … /* LCD Raster Timing 2 Register */ #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) … #define LCD_AC_BIAS_FREQUENCY(x) … #define LCD_SYNC_CTRL … #define LCD_SYNC_EDGE … #define LCD_INVERT_PIXEL_CLOCK … #define LCD_INVERT_LINE_CLOCK … #define LCD_INVERT_FRAME_CLOCK … /* LCD Block */ #define LCD_PID_REG … #define LCD_CTRL_REG … #define LCD_STAT_REG … #define LCD_RASTER_CTRL_REG … #define LCD_RASTER_TIMING_0_REG … #define LCD_RASTER_TIMING_1_REG … #define LCD_RASTER_TIMING_2_REG … #define LCD_DMA_CTRL_REG … #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG … #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG … #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG … #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG … /* Interrupt Registers available only in Version 2 */ #define LCD_RAW_STAT_REG … #define LCD_MASKED_STAT_REG … #define LCD_INT_ENABLE_SET_REG … #define LCD_INT_ENABLE_CLR_REG … #define LCD_END_OF_INT_IND_REG … /* Clock registers available only on Version 2 */ #define LCD_CLK_ENABLE_REG … #define LCD_CLK_RESET_REG … #define LCD_CLK_MAIN_RESET … #define LCD_NUM_BUFFERS … #define PALETTE_SIZE … #define CLK_MIN_DIV … #define CLK_MAX_DIV … static void __iomem *da8xx_fb_reg_base; static unsigned int lcd_revision; static irq_handler_t lcdc_irq_handler; static wait_queue_head_t frame_done_wq; static int frame_done_flag; static unsigned int lcdc_read(unsigned int addr) { … } static void lcdc_write(unsigned int val, unsigned int addr) { … } struct da8xx_fb_par { … }; static struct fb_var_screeninfo da8xx_fb_var; static struct fb_fix_screeninfo da8xx_fb_fix = …; static struct fb_videomode known_lcd_panels[] = …; static bool da8xx_fb_is_raster_enabled(void) { … } /* Enable the Raster Engine of the LCD Controller */ static void lcd_enable_raster(void) { … } /* Disable the Raster Engine of the LCD Controller */ static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done) { … } static void lcd_blit(int load_mode, struct da8xx_fb_par *par) { … } /* Configure the Burst Size and fifo threhold of DMA */ static int lcd_cfg_dma(int burst_size, int fifo_th) { … } static void lcd_cfg_ac_bias(int period, int transitions_per_int) { … } static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, int front_porch) { … } static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, int front_porch) { … } static int lcd_cfg_display(const struct lcd_ctrl_config *cfg, struct fb_videomode *panel) { … } static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, u32 bpp, u32 raster_order) { … } #define CNVT_TOHW … static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) { … } #undef CNVT_TOHW static void da8xx_fb_lcd_reset(void) { … } static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par, unsigned lcdc_clk_div, unsigned lcdc_clk_rate) { … } static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par, unsigned pixclock, unsigned *lcdc_clk_rate) { … } static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par, struct fb_videomode *mode) { … } static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par, unsigned pixclock) { … } static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, struct fb_videomode *panel) { … } /* IRQ handler for version 2 of LCDC */ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) { … } /* IRQ handler for version 1 LCDC */ static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) { … } static int fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { … } #ifdef CONFIG_CPU_FREQ static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data) { … } static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) { … } static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) { … } #endif static void fb_remove(struct platform_device *dev) { … } /* * Function to wait for vertical sync which for this LCD peripheral * translates into waiting for the current raster frame to complete. */ static int fb_wait_for_vsync(struct fb_info *info) { … } static int fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) { … } static int cfb_blank(int blank, struct fb_info *info) { … } /* * Set new x,y offsets in the virtual display for the visible area and switch * to the new mode. */ static int da8xx_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi) { … } static int da8xxfb_set_par(struct fb_info *info) { … } static const struct fb_ops da8xx_fb_ops = …; static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev) { … } static int fb_probe(struct platform_device *device) { … } #ifdef CONFIG_PM_SLEEP static struct lcdc_context { … } reg_context; static void lcd_context_save(void) { … } static void lcd_context_restore(void) { … } static int fb_suspend(struct device *dev) { … } static int fb_resume(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(fb_pm_ops, fb_suspend, fb_resume); static struct platform_driver da8xx_fb_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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