/* * Copyright © 2008 Keith Packard * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of the copyright holders not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. The copyright holders make no representations * about the suitability of this software for any purpose. It is provided "as * is" without express or implied warranty. * * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE * OF THIS SOFTWARE. */ #ifndef _DRM_DP_H_ #define _DRM_DP_H_ #include <linux/types.h> /* * Unless otherwise noted, all values are from the DP 1.1a spec. Note that * DP and DPCD versions are independent. Differences from 1.0 are not noted, * 1.0 devices basically don't exist in the wild. * * Abbreviations, in chronological order: * * eDP: Embedded DisplayPort version 1 * DPI: DisplayPort Interoperability Guideline v1.1a * 1.2: DisplayPort 1.2 * MST: Multistream Transport - part of DP 1.2a * * 1.2 formally includes both eDP and DPI definitions. */ /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */ #define DP_MSA_MISC_SYNC_CLOCK … #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN … #define DP_MSA_MISC_STEREO_NO_3D … #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE … #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE … /* bits per component for non-RAW */ #define DP_MSA_MISC_6_BPC … #define DP_MSA_MISC_8_BPC … #define DP_MSA_MISC_10_BPC … #define DP_MSA_MISC_12_BPC … #define DP_MSA_MISC_16_BPC … /* bits per component for RAW */ #define DP_MSA_MISC_RAW_6_BPC … #define DP_MSA_MISC_RAW_7_BPC … #define DP_MSA_MISC_RAW_8_BPC … #define DP_MSA_MISC_RAW_10_BPC … #define DP_MSA_MISC_RAW_12_BPC … #define DP_MSA_MISC_RAW_14_BPC … #define DP_MSA_MISC_RAW_16_BPC … /* pixel encoding/colorimetry format */ #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) … #define DP_MSA_MISC_COLOR_RGB … #define DP_MSA_MISC_COLOR_CEA_RGB … #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED … #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT … #define DP_MSA_MISC_COLOR_Y_ONLY … #define DP_MSA_MISC_COLOR_RAW … #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 … #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 … #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 … #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 … #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 … #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 … #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 … #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 … #define DP_MSA_MISC_COLOR_OPRGB … #define DP_MSA_MISC_COLOR_DCI_P3 … #define DP_MSA_MISC_COLOR_COLOR_PROFILE … #define DP_MSA_MISC_COLOR_VSC_SDP … #define DP_AUX_MAX_PAYLOAD_BYTES … #define DP_AUX_I2C_WRITE … #define DP_AUX_I2C_READ … #define DP_AUX_I2C_WRITE_STATUS_UPDATE … #define DP_AUX_I2C_MOT … #define DP_AUX_NATIVE_WRITE … #define DP_AUX_NATIVE_READ … #define DP_AUX_NATIVE_REPLY_ACK … #define DP_AUX_NATIVE_REPLY_NACK … #define DP_AUX_NATIVE_REPLY_DEFER … #define DP_AUX_NATIVE_REPLY_MASK … #define DP_AUX_I2C_REPLY_ACK … #define DP_AUX_I2C_REPLY_NACK … #define DP_AUX_I2C_REPLY_DEFER … #define DP_AUX_I2C_REPLY_MASK … /* DPCD Field Address Mapping */ /* Receiver Capability */ #define DP_DPCD_REV … #define DP_DPCD_REV_10 … #define DP_DPCD_REV_11 … #define DP_DPCD_REV_12 … #define DP_DPCD_REV_13 … #define DP_DPCD_REV_14 … #define DP_MAX_LINK_RATE … #define DP_MAX_LANE_COUNT … #define DP_MAX_LANE_COUNT_MASK … #define DP_TPS3_SUPPORTED … #define DP_ENHANCED_FRAME_CAP … #define DP_MAX_DOWNSPREAD … #define DP_MAX_DOWNSPREAD_0_5 … #define DP_STREAM_REGENERATION_STATUS_CAP … #define DP_NO_AUX_HANDSHAKE_LINK_TRAINING … #define DP_TPS4_SUPPORTED … #define DP_NORP … #define DP_DOWNSTREAMPORT_PRESENT … #define DP_DWN_STRM_PORT_PRESENT … #define DP_DWN_STRM_PORT_TYPE_MASK … #define DP_DWN_STRM_PORT_TYPE_DP … #define DP_DWN_STRM_PORT_TYPE_ANALOG … #define DP_DWN_STRM_PORT_TYPE_TMDS … #define DP_DWN_STRM_PORT_TYPE_OTHER … #define DP_FORMAT_CONVERSION … #define DP_DETAILED_CAP_INFO_AVAILABLE … #define DP_MAIN_LINK_CHANNEL_CODING … #define DP_CAP_ANSI_8B10B … #define DP_CAP_ANSI_128B132B … #define DP_DOWN_STREAM_PORT_COUNT … #define DP_PORT_COUNT_MASK … #define DP_MSA_TIMING_PAR_IGNORED … #define DP_OUI_SUPPORT … #define DP_RECEIVE_PORT_0_CAP_0 … #define DP_LOCAL_EDID_PRESENT … #define DP_ASSOCIATED_TO_PRECEDING_PORT … #define DP_HBLANK_EXPANSION_CAPABLE … #define DP_RECEIVE_PORT_0_BUFFER_SIZE … #define DP_RECEIVE_PORT_1_CAP_0 … #define DP_RECEIVE_PORT_1_BUFFER_SIZE … #define DP_I2C_SPEED_CAP … #define DP_I2C_SPEED_1K … #define DP_I2C_SPEED_5K … #define DP_I2C_SPEED_10K … #define DP_I2C_SPEED_100K … #define DP_I2C_SPEED_400K … #define DP_I2C_SPEED_1M … #define DP_EDP_CONFIGURATION_CAP … #define DP_ALTERNATE_SCRAMBLER_RESET_CAP … #define DP_FRAMING_CHANGE_CAP … #define DP_DPCD_DISPLAY_CONTROL_CAPABLE … #define DP_TRAINING_AUX_RD_INTERVAL … #define DP_TRAINING_AUX_RD_MASK … #define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT … #define DP_ADAPTER_CAP … #define DP_FORCE_LOAD_SENSE_CAP … #define DP_ALTERNATE_I2C_PATTERN_CAP … #define DP_SUPPORTED_LINK_RATES … #define DP_MAX_SUPPORTED_RATES … /* Multiple stream transport */ #define DP_FAUX_CAP … #define DP_FAUX_CAP_1 … #define DP_SINK_VIDEO_FALLBACK_FORMATS … #define DP_FALLBACK_1024x768_60HZ_24BPP … #define DP_FALLBACK_1280x720_60HZ_24BPP … #define DP_FALLBACK_1920x1080_60HZ_24BPP … #define DP_MSTM_CAP … #define DP_MST_CAP … #define DP_SINGLE_STREAM_SIDEBAND_MSG … #define DP_NUMBER_OF_AUDIO_ENDPOINTS … /* AV_SYNC_DATA_BLOCK 1.2 */ #define DP_AV_GRANULARITY … #define DP_AG_FACTOR_MASK … #define DP_AG_FACTOR_3MS … #define DP_AG_FACTOR_2MS … #define DP_AG_FACTOR_1MS … #define DP_AG_FACTOR_500US … #define DP_AG_FACTOR_200US … #define DP_AG_FACTOR_100US … #define DP_AG_FACTOR_10US … #define DP_AG_FACTOR_1US … #define DP_VG_FACTOR_MASK … #define DP_VG_FACTOR_3MS … #define DP_VG_FACTOR_2MS … #define DP_VG_FACTOR_1MS … #define DP_VG_FACTOR_500US … #define DP_VG_FACTOR_200US … #define DP_VG_FACTOR_100US … #define DP_AUD_DEC_LAT0 … #define DP_AUD_DEC_LAT1 … #define DP_AUD_PP_LAT0 … #define DP_AUD_PP_LAT1 … #define DP_VID_INTER_LAT … #define DP_VID_PROG_LAT … #define DP_REP_LAT … #define DP_AUD_DEL_INS0 … #define DP_AUD_DEL_INS1 … #define DP_AUD_DEL_INS2 … /* End of AV_SYNC_DATA_BLOCK */ #define DP_RECEIVER_ALPM_CAP … #define DP_ALPM_CAP … #define DP_ALPM_PM_STATE_2A_SUPPORT … #define DP_ALPM_AUX_LESS_CAP … #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP … #define DP_AUX_FRAME_SYNC_CAP … #define DP_GUID … #define DP_DSC_SUPPORT … #define DP_DSC_DECOMPRESSION_IS_SUPPORTED … #define DP_DSC_PASSTHROUGH_IS_SUPPORTED … #define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP … #define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP … #define DP_DSC_REV … #define DP_DSC_MAJOR_MASK … #define DP_DSC_MINOR_MASK … #define DP_DSC_MAJOR_SHIFT … #define DP_DSC_MINOR_SHIFT … #define DP_DSC_RC_BUF_BLK_SIZE … #define DP_DSC_RC_BUF_BLK_SIZE_1 … #define DP_DSC_RC_BUF_BLK_SIZE_4 … #define DP_DSC_RC_BUF_BLK_SIZE_16 … #define DP_DSC_RC_BUF_BLK_SIZE_64 … #define DP_DSC_RC_BUF_SIZE … #define DP_DSC_SLICE_CAP_1 … #define DP_DSC_1_PER_DP_DSC_SINK … #define DP_DSC_2_PER_DP_DSC_SINK … #define DP_DSC_4_PER_DP_DSC_SINK … #define DP_DSC_6_PER_DP_DSC_SINK … #define DP_DSC_8_PER_DP_DSC_SINK … #define DP_DSC_10_PER_DP_DSC_SINK … #define DP_DSC_12_PER_DP_DSC_SINK … #define DP_DSC_LINE_BUF_BIT_DEPTH … #define DP_DSC_LINE_BUF_BIT_DEPTH_MASK … #define DP_DSC_LINE_BUF_BIT_DEPTH_9 … #define DP_DSC_LINE_BUF_BIT_DEPTH_10 … #define DP_DSC_LINE_BUF_BIT_DEPTH_11 … #define DP_DSC_LINE_BUF_BIT_DEPTH_12 … #define DP_DSC_LINE_BUF_BIT_DEPTH_13 … #define DP_DSC_LINE_BUF_BIT_DEPTH_14 … #define DP_DSC_LINE_BUF_BIT_DEPTH_15 … #define DP_DSC_LINE_BUF_BIT_DEPTH_16 … #define DP_DSC_LINE_BUF_BIT_DEPTH_8 … #define DP_DSC_BLK_PREDICTION_SUPPORT … #define DP_DSC_BLK_PREDICTION_IS_SUPPORTED … #define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT … #define DP_DSC_MAX_BITS_PER_PIXEL_LOW … #define DP_DSC_MAX_BITS_PER_PIXEL_HI … #define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK … #define DP_DSC_MAX_BPP_DELTA_VERSION_MASK … #define DP_DSC_MAX_BPP_DELTA_AVAILABILITY … #define DP_DSC_DEC_COLOR_FORMAT_CAP … #define DP_DSC_RGB … #define DP_DSC_YCbCr444 … #define DP_DSC_YCbCr422_Simple … #define DP_DSC_YCbCr422_Native … #define DP_DSC_YCbCr420_Native … #define DP_DSC_DEC_COLOR_DEPTH_CAP … #define DP_DSC_8_BPC … #define DP_DSC_10_BPC … #define DP_DSC_12_BPC … #define DP_DSC_PEAK_THROUGHPUT … #define DP_DSC_THROUGHPUT_MODE_0_MASK … #define DP_DSC_THROUGHPUT_MODE_0_SHIFT … #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED … #define DP_DSC_THROUGHPUT_MODE_0_340 … #define DP_DSC_THROUGHPUT_MODE_0_400 … #define DP_DSC_THROUGHPUT_MODE_0_450 … #define DP_DSC_THROUGHPUT_MODE_0_500 … #define DP_DSC_THROUGHPUT_MODE_0_550 … #define DP_DSC_THROUGHPUT_MODE_0_600 … #define DP_DSC_THROUGHPUT_MODE_0_650 … #define DP_DSC_THROUGHPUT_MODE_0_700 … #define DP_DSC_THROUGHPUT_MODE_0_750 … #define DP_DSC_THROUGHPUT_MODE_0_800 … #define DP_DSC_THROUGHPUT_MODE_0_850 … #define DP_DSC_THROUGHPUT_MODE_0_900 … #define DP_DSC_THROUGHPUT_MODE_0_950 … #define DP_DSC_THROUGHPUT_MODE_0_1000 … #define DP_DSC_THROUGHPUT_MODE_0_170 … #define DP_DSC_THROUGHPUT_MODE_1_MASK … #define DP_DSC_THROUGHPUT_MODE_1_SHIFT … #define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED … #define DP_DSC_THROUGHPUT_MODE_1_340 … #define DP_DSC_THROUGHPUT_MODE_1_400 … #define DP_DSC_THROUGHPUT_MODE_1_450 … #define DP_DSC_THROUGHPUT_MODE_1_500 … #define DP_DSC_THROUGHPUT_MODE_1_550 … #define DP_DSC_THROUGHPUT_MODE_1_600 … #define DP_DSC_THROUGHPUT_MODE_1_650 … #define DP_DSC_THROUGHPUT_MODE_1_700 … #define DP_DSC_THROUGHPUT_MODE_1_750 … #define DP_DSC_THROUGHPUT_MODE_1_800 … #define DP_DSC_THROUGHPUT_MODE_1_850 … #define DP_DSC_THROUGHPUT_MODE_1_900 … #define DP_DSC_THROUGHPUT_MODE_1_950 … #define DP_DSC_THROUGHPUT_MODE_1_1000 … #define DP_DSC_THROUGHPUT_MODE_1_170 … #define DP_DSC_MAX_SLICE_WIDTH … #define DP_DSC_MIN_SLICE_WIDTH_VALUE … #define DP_DSC_SLICE_WIDTH_MULTIPLIER … #define DP_DSC_SLICE_CAP_2 … #define DP_DSC_16_PER_DP_DSC_SINK … #define DP_DSC_20_PER_DP_DSC_SINK … #define DP_DSC_24_PER_DP_DSC_SINK … #define DP_DSC_BITS_PER_PIXEL_INC … #define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK … #define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK … #define DP_DSC_BITS_PER_PIXEL_1_16 … #define DP_DSC_BITS_PER_PIXEL_1_8 … #define DP_DSC_BITS_PER_PIXEL_1_4 … #define DP_DSC_BITS_PER_PIXEL_1_2 … #define DP_DSC_BITS_PER_PIXEL_1_1 … #define DP_PSR_SUPPORT … #define DP_PSR_IS_SUPPORTED … #define DP_PSR2_IS_SUPPORTED … #define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED … #define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED … #define DP_PSR_CAPS … #define DP_PSR_NO_TRAIN_ON_EXIT … #define DP_PSR_SETUP_TIME_330 … #define DP_PSR_SETUP_TIME_275 … #define DP_PSR_SETUP_TIME_220 … #define DP_PSR_SETUP_TIME_165 … #define DP_PSR_SETUP_TIME_110 … #define DP_PSR_SETUP_TIME_55 … #define DP_PSR_SETUP_TIME_0 … #define DP_PSR_SETUP_TIME_MASK … #define DP_PSR_SETUP_TIME_SHIFT … #define DP_PSR2_SU_Y_COORDINATE_REQUIRED … #define DP_PSR2_SU_GRANULARITY_REQUIRED … #define DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED … #define DP_PSR2_SU_X_GRANULARITY … #define DP_PSR2_SU_Y_GRANULARITY … /* * 0x80-0x8f describe downstream port capabilities, but there are two layouts * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, * each port's descriptor is one byte wide. If it was set, each port's is * four bytes wide, starting with the one byte from the base info. As of * DP interop v1.1a only VGA defines additional detail. */ /* offset 0 */ #define DP_DOWNSTREAM_PORT_0 … #define DP_DS_PORT_TYPE_MASK … #define DP_DS_PORT_TYPE_DP … #define DP_DS_PORT_TYPE_VGA … #define DP_DS_PORT_TYPE_DVI … #define DP_DS_PORT_TYPE_HDMI … #define DP_DS_PORT_TYPE_NON_EDID … #define DP_DS_PORT_TYPE_DP_DUALMODE … #define DP_DS_PORT_TYPE_WIRELESS … #define DP_DS_PORT_HPD … #define DP_DS_NON_EDID_MASK … #define DP_DS_NON_EDID_720x480i_60 … #define DP_DS_NON_EDID_720x480i_50 … #define DP_DS_NON_EDID_1920x1080i_60 … #define DP_DS_NON_EDID_1920x1080i_50 … #define DP_DS_NON_EDID_1280x720_60 … #define DP_DS_NON_EDID_1280x720_50 … /* offset 1 for VGA is maximum megapixels per second / 8 */ /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */ /* offset 2 for VGA/DVI/HDMI */ #define DP_DS_MAX_BPC_MASK … #define DP_DS_8BPC … #define DP_DS_10BPC … #define DP_DS_12BPC … #define DP_DS_16BPC … /* HDMI2.1 PCON FRL CONFIGURATION */ #define DP_PCON_MAX_FRL_BW … #define DP_PCON_MAX_0GBPS … #define DP_PCON_MAX_9GBPS … #define DP_PCON_MAX_18GBPS … #define DP_PCON_MAX_24GBPS … #define DP_PCON_MAX_32GBPS … #define DP_PCON_MAX_40GBPS … #define DP_PCON_MAX_48GBPS … #define DP_PCON_SOURCE_CTL_MODE … /* offset 3 for DVI */ #define DP_DS_DVI_DUAL_LINK … #define DP_DS_DVI_HIGH_COLOR_DEPTH … /* offset 3 for HDMI */ #define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK … #define DP_DS_HDMI_YCBCR422_PASS_THROUGH … #define DP_DS_HDMI_YCBCR420_PASS_THROUGH … #define DP_DS_HDMI_YCBCR444_TO_422_CONV … #define DP_DS_HDMI_YCBCR444_TO_420_CONV … /* * VESA DP-to-HDMI PCON Specification adds caps for colorspace * conversion in DFP cap DPCD 83h. Sec6.1 Table-3. * Based on the available support the source can enable * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2 * DPCD 3052h. */ #define DP_DS_HDMI_BT601_RGB_YCBCR_CONV … #define DP_DS_HDMI_BT709_RGB_YCBCR_CONV … #define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV … #define DP_MAX_DOWNSTREAM_PORTS … /* DP Forward error Correction Registers */ #define DP_FEC_CAPABILITY … #define DP_FEC_CAPABLE … #define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP … #define DP_FEC_CORR_BLK_ERROR_COUNT_CAP … #define DP_FEC_BIT_ERROR_COUNT_CAP … #define DP_FEC_CAPABILITY_1 … /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ #define DP_PCON_DSC_ENCODER_CAP_SIZE … #define DP_PCON_DSC_ENCODER … #define DP_PCON_DSC_ENCODER_SUPPORTED … #define DP_PCON_DSC_PPS_ENC_OVERRIDE … /* DP-HDMI2.1 PCON DSC Version */ #define DP_PCON_DSC_VERSION … #define DP_PCON_DSC_MAJOR_MASK … #define DP_PCON_DSC_MINOR_MASK … #define DP_PCON_DSC_MAJOR_SHIFT … #define DP_PCON_DSC_MINOR_SHIFT … /* DP-HDMI2.1 PCON DSC RC Buffer block size */ #define DP_PCON_DSC_RC_BUF_BLK_INFO … #define DP_PCON_DSC_RC_BUF_BLK_SIZE … #define DP_PCON_DSC_RC_BUF_BLK_1KB … #define DP_PCON_DSC_RC_BUF_BLK_4KB … #define DP_PCON_DSC_RC_BUF_BLK_16KB … #define DP_PCON_DSC_RC_BUF_BLK_64KB … /* DP-HDMI2.1 PCON DSC RC Buffer size */ #define DP_PCON_DSC_RC_BUF_SIZE … /* DP-HDMI2.1 PCON DSC Slice capabilities-1 */ #define DP_PCON_DSC_SLICE_CAP_1 … #define DP_PCON_DSC_1_PER_DSC_ENC … #define DP_PCON_DSC_2_PER_DSC_ENC … #define DP_PCON_DSC_4_PER_DSC_ENC … #define DP_PCON_DSC_6_PER_DSC_ENC … #define DP_PCON_DSC_8_PER_DSC_ENC … #define DP_PCON_DSC_10_PER_DSC_ENC … #define DP_PCON_DSC_12_PER_DSC_ENC … #define DP_PCON_DSC_BUF_BIT_DEPTH … #define DP_PCON_DSC_BIT_DEPTH_MASK … #define DP_PCON_DSC_DEPTH_9_BITS … #define DP_PCON_DSC_DEPTH_10_BITS … #define DP_PCON_DSC_DEPTH_11_BITS … #define DP_PCON_DSC_DEPTH_12_BITS … #define DP_PCON_DSC_DEPTH_13_BITS … #define DP_PCON_DSC_DEPTH_14_BITS … #define DP_PCON_DSC_DEPTH_15_BITS … #define DP_PCON_DSC_DEPTH_16_BITS … #define DP_PCON_DSC_DEPTH_8_BITS … #define DP_PCON_DSC_BLOCK_PREDICTION … #define DP_PCON_DSC_BLOCK_PRED_SUPPORT … #define DP_PCON_DSC_ENC_COLOR_FMT_CAP … #define DP_PCON_DSC_ENC_RGB … #define DP_PCON_DSC_ENC_YUV444 … #define DP_PCON_DSC_ENC_YUV422_S … #define DP_PCON_DSC_ENC_YUV422_N … #define DP_PCON_DSC_ENC_YUV420_N … #define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP … #define DP_PCON_DSC_ENC_8BPC … #define DP_PCON_DSC_ENC_10BPC … #define DP_PCON_DSC_ENC_12BPC … #define DP_PCON_DSC_MAX_SLICE_WIDTH … /* DP-HDMI2.1 PCON DSC Slice capabilities-2 */ #define DP_PCON_DSC_SLICE_CAP_2 … #define DP_PCON_DSC_16_PER_DSC_ENC … #define DP_PCON_DSC_20_PER_DSC_ENC … #define DP_PCON_DSC_24_PER_DSC_ENC … /* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */ #define DP_PCON_DSC_BPP_INCR … #define DP_PCON_DSC_BPP_INCR_MASK … #define DP_PCON_DSC_ONE_16TH_BPP … #define DP_PCON_DSC_ONE_8TH_BPP … #define DP_PCON_DSC_ONE_4TH_BPP … #define DP_PCON_DSC_ONE_HALF_BPP … #define DP_PCON_DSC_ONE_BPP … /* DP Extended DSC Capabilities */ #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 … #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 … #define DP_DSC_BRANCH_MAX_LINE_WIDTH … /* DFP Capability Extension */ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT … #define DP_PANEL_REPLAY_CAP … #define DP_PANEL_REPLAY_SUPPORT … #define DP_PANEL_REPLAY_SU_SUPPORT … #define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT … #define DP_PANEL_PANEL_REPLAY_CAPABILITY … #define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED … #define DP_PANEL_PANEL_REPLAY_X_GRANULARITY … #define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY … /* Link Configuration */ #define DP_LINK_BW_SET … #define DP_LINK_RATE_TABLE … #define DP_LINK_BW_1_62 … #define DP_LINK_BW_2_7 … #define DP_LINK_BW_5_4 … #define DP_LINK_BW_8_1 … #define DP_LINK_BW_10 … #define DP_LINK_BW_13_5 … #define DP_LINK_BW_20 … #define DP_LANE_COUNT_SET … #define DP_LANE_COUNT_MASK … #define DP_LANE_COUNT_ENHANCED_FRAME_EN … #define DP_TRAINING_PATTERN_SET … #define DP_TRAINING_PATTERN_DISABLE … #define DP_TRAINING_PATTERN_1 … #define DP_TRAINING_PATTERN_2 … #define DP_TRAINING_PATTERN_2_CDS … #define DP_TRAINING_PATTERN_3 … #define DP_TRAINING_PATTERN_4 … #define DP_TRAINING_PATTERN_MASK … #define DP_TRAINING_PATTERN_MASK_1_4 … /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ #define DP_LINK_QUAL_PATTERN_11_DISABLE … #define DP_LINK_QUAL_PATTERN_11_D10_2 … #define DP_LINK_QUAL_PATTERN_11_ERROR_RATE … #define DP_LINK_QUAL_PATTERN_11_PRBS7 … #define DP_LINK_QUAL_PATTERN_11_MASK … #define DP_RECOVERED_CLOCK_OUT_EN … #define DP_LINK_SCRAMBLING_DISABLE … #define DP_SYMBOL_ERROR_COUNT_BOTH … #define DP_SYMBOL_ERROR_COUNT_DISPARITY … #define DP_SYMBOL_ERROR_COUNT_SYMBOL … #define DP_SYMBOL_ERROR_COUNT_MASK … #define DP_TRAINING_LANE0_SET … #define DP_TRAINING_LANE1_SET … #define DP_TRAINING_LANE2_SET … #define DP_TRAINING_LANE3_SET … #define DP_TRAIN_VOLTAGE_SWING_MASK … #define DP_TRAIN_VOLTAGE_SWING_SHIFT … #define DP_TRAIN_MAX_SWING_REACHED … #define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 … #define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 … #define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 … #define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 … #define DP_TRAIN_PRE_EMPHASIS_MASK … #define DP_TRAIN_PRE_EMPH_LEVEL_0 … #define DP_TRAIN_PRE_EMPH_LEVEL_1 … #define DP_TRAIN_PRE_EMPH_LEVEL_2 … #define DP_TRAIN_PRE_EMPH_LEVEL_3 … #define DP_TRAIN_PRE_EMPHASIS_SHIFT … #define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED … #define DP_TX_FFE_PRESET_VALUE_MASK … #define DP_DOWNSPREAD_CTRL … #define DP_SPREAD_AMP_0_5 … #define DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE … #define DP_MSA_TIMING_PAR_IGNORE_EN … #define DP_MAIN_LINK_CHANNEL_CODING_SET … #define DP_SET_ANSI_8B10B … #define DP_SET_ANSI_128B132B … #define DP_I2C_SPEED_CONTROL_STATUS … /* bitmask as for DP_I2C_SPEED_CAP */ #define DP_EDP_CONFIGURATION_SET … #define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE … #define DP_FRAMING_CHANGE_ENABLE … #define DP_PANEL_SELF_TEST_ENABLE … #define DP_LINK_QUAL_LANE0_SET … #define DP_LINK_QUAL_LANE1_SET … #define DP_LINK_QUAL_LANE2_SET … #define DP_LINK_QUAL_LANE3_SET … #define DP_LINK_QUAL_PATTERN_DISABLE … #define DP_LINK_QUAL_PATTERN_D10_2 … #define DP_LINK_QUAL_PATTERN_ERROR_RATE … #define DP_LINK_QUAL_PATTERN_PRBS7 … #define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM … #define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 … #define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 … #define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 … /* DP 2.0 UHBR10, UHBR13.5, UHBR20 */ #define DP_LINK_QUAL_PATTERN_128B132B_TPS1 … #define DP_LINK_QUAL_PATTERN_128B132B_TPS2 … #define DP_LINK_QUAL_PATTERN_PRSBS9 … #define DP_LINK_QUAL_PATTERN_PRSBS11 … #define DP_LINK_QUAL_PATTERN_PRSBS15 … #define DP_LINK_QUAL_PATTERN_PRSBS23 … #define DP_LINK_QUAL_PATTERN_PRSBS31 … #define DP_LINK_QUAL_PATTERN_CUSTOM … #define DP_LINK_QUAL_PATTERN_SQUARE … #define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DISABLED … #define DP_LINK_QUAL_PATTERN_SQUARE_DEEMPHASIS_DISABLED … #define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED … #define DP_TRAINING_LANE0_1_SET2 … #define DP_TRAINING_LANE2_3_SET2 … #define DP_LANE02_POST_CURSOR2_SET_MASK … #define DP_LANE02_MAX_POST_CURSOR2_REACHED … #define DP_LANE13_POST_CURSOR2_SET_MASK … #define DP_LANE13_MAX_POST_CURSOR2_REACHED … #define DP_MSTM_CTRL … #define DP_MST_EN … #define DP_UP_REQ_EN … #define DP_UPSTREAM_IS_SRC … #define DP_AUDIO_DELAY0 … #define DP_AUDIO_DELAY1 … #define DP_AUDIO_DELAY2 … #define DP_LINK_RATE_SET … #define DP_LINK_RATE_SET_SHIFT … #define DP_LINK_RATE_SET_MASK … #define DP_RECEIVER_ALPM_CONFIG … #define DP_ALPM_ENABLE … #define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE … #define DP_ALPM_MODE_AUX_LESS … #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF … #define DP_AUX_FRAME_SYNC_ENABLE … #define DP_IRQ_HPD_ENABLE … #define DP_UPSTREAM_DEVICE_DP_PWR_NEED … #define DP_PWR_NOT_NEEDED … #define DP_FEC_CONFIGURATION … #define DP_FEC_READY … #define DP_FEC_ERR_COUNT_SEL_MASK … #define DP_FEC_ERR_COUNT_DIS … #define DP_FEC_UNCORR_BLK_ERROR_COUNT … #define DP_FEC_CORR_BLK_ERROR_COUNT … #define DP_FEC_BIT_ERROR_COUNT … #define DP_FEC_LANE_SELECT_MASK … #define DP_FEC_LANE_0_SELECT … #define DP_FEC_LANE_1_SELECT … #define DP_FEC_LANE_2_SELECT … #define DP_FEC_LANE_3_SELECT … #define DP_SDP_ERROR_DETECTION_CONFIGURATION … #define DP_SDP_CRC16_128B132B_EN … #define DP_AUX_FRAME_SYNC_VALUE … #define DP_AUX_FRAME_SYNC_VALID … #define DP_DSC_ENABLE … #define DP_DECOMPRESSION_EN … #define DP_DSC_PASSTHROUGH_EN … #define DP_DSC_CONFIGURATION … #define DP_PSR_EN_CFG … #define DP_PSR_ENABLE … #define DP_PSR_MAIN_LINK_ACTIVE … #define DP_PSR_CRC_VERIFICATION … #define DP_PSR_FRAME_CAPTURE … #define DP_PSR_SU_REGION_SCANLINE_CAPTURE … #define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS … #define DP_PSR_ENABLE_PSR2 … #define DP_PSR_ENABLE_SU_REGION_ET … #define DP_ADAPTER_CTRL … #define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE … #define DP_BRANCH_DEVICE_CTRL … #define DP_BRANCH_DEVICE_IRQ_HPD … #define PANEL_REPLAY_CONFIG … #define DP_PANEL_REPLAY_ENABLE … #define DP_PANEL_REPLAY_VSC_SDP_CRC_EN … #define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN … #define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN … #define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN … #define DP_PANEL_REPLAY_SU_ENABLE … #define DP_PANEL_REPLAY_ENABLE_SU_REGION_ET … #define PANEL_REPLAY_CONFIG2 … #define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED … #define DP_PANEL_REPLAY_CRC_VERIFICATION … #define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN … #define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT … #define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK … #define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE … #define DP_PAYLOAD_ALLOCATE_SET … #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT … #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT … /* Link/Sink Device Status */ #define DP_SINK_COUNT … /* prior to 1.2 bit 7 was reserved mbz */ #define DP_GET_SINK_COUNT(x) … #define DP_SINK_CP_READY … #define DP_DEVICE_SERVICE_IRQ_VECTOR … #define DP_REMOTE_CONTROL_COMMAND_PENDING … #define DP_AUTOMATED_TEST_REQUEST … #define DP_CP_IRQ … #define DP_MCCS_IRQ … #define DP_DOWN_REP_MSG_RDY … #define DP_UP_REQ_MSG_RDY … #define DP_SINK_SPECIFIC_IRQ … #define DP_LANE0_1_STATUS … #define DP_LANE2_3_STATUS … #define DP_LANE_CR_DONE … #define DP_LANE_CHANNEL_EQ_DONE … #define DP_LANE_SYMBOL_LOCKED … #define DP_CHANNEL_EQ_BITS … #define DP_LANE_ALIGN_STATUS_UPDATED … #define DP_INTERLANE_ALIGN_DONE … #define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE … #define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE … #define DP_128B132B_LT_FAILED … #define DP_DOWNSTREAM_PORT_STATUS_CHANGED … #define DP_LINK_STATUS_UPDATED … #define DP_SINK_STATUS … #define DP_RECEIVE_PORT_0_STATUS … #define DP_RECEIVE_PORT_1_STATUS … #define DP_STREAM_REGENERATION_STATUS … #define DP_INTRA_HOP_AUX_REPLY_INDICATION … #define DP_ADJUST_REQUEST_LANE0_1 … #define DP_ADJUST_REQUEST_LANE2_3 … #define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK … #define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT … #define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK … #define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT … #define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK … #define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT … #define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK … #define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT … /* DP 2.0 128b/132b Link Layer */ #define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK … #define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT … #define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK … #define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT … #define DP_ADJUST_REQUEST_POST_CURSOR2 … #define DP_ADJUST_POST_CURSOR2_LANE0_MASK … #define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT … #define DP_ADJUST_POST_CURSOR2_LANE1_MASK … #define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT … #define DP_ADJUST_POST_CURSOR2_LANE2_MASK … #define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT … #define DP_ADJUST_POST_CURSOR2_LANE3_MASK … #define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT … #define DP_TEST_REQUEST … #define DP_TEST_LINK_TRAINING … #define DP_TEST_LINK_VIDEO_PATTERN … #define DP_TEST_LINK_EDID_READ … #define DP_TEST_LINK_PHY_TEST_PATTERN … #define DP_TEST_LINK_FAUX_PATTERN … #define DP_TEST_LINK_AUDIO_PATTERN … #define DP_TEST_LINK_AUDIO_DISABLED_VIDEO … #define DP_TEST_LINK_RATE … #define DP_LINK_RATE_162 … #define DP_LINK_RATE_27 … #define DP_TEST_LANE_COUNT … #define DP_TEST_PATTERN … #define DP_NO_TEST_PATTERN … #define DP_COLOR_RAMP … #define DP_BLACK_AND_WHITE_VERTICAL_LINES … #define DP_COLOR_SQUARE … #define DP_TEST_H_TOTAL_HI … #define DP_TEST_H_TOTAL_LO … #define DP_TEST_V_TOTAL_HI … #define DP_TEST_V_TOTAL_LO … #define DP_TEST_H_START_HI … #define DP_TEST_H_START_LO … #define DP_TEST_V_START_HI … #define DP_TEST_V_START_LO … #define DP_TEST_HSYNC_HI … #define DP_TEST_HSYNC_POLARITY … #define DP_TEST_HSYNC_WIDTH_HI_MASK … #define DP_TEST_HSYNC_WIDTH_LO … #define DP_TEST_VSYNC_HI … #define DP_TEST_VSYNC_POLARITY … #define DP_TEST_VSYNC_WIDTH_HI_MASK … #define DP_TEST_VSYNC_WIDTH_LO … #define DP_TEST_H_WIDTH_HI … #define DP_TEST_H_WIDTH_LO … #define DP_TEST_V_HEIGHT_HI … #define DP_TEST_V_HEIGHT_LO … #define DP_TEST_MISC0 … #define DP_TEST_SYNC_CLOCK … #define DP_TEST_COLOR_FORMAT_MASK … #define DP_TEST_COLOR_FORMAT_SHIFT … #define DP_COLOR_FORMAT_RGB … #define DP_COLOR_FORMAT_YCbCr422 … #define DP_COLOR_FORMAT_YCbCr444 … #define DP_TEST_DYNAMIC_RANGE_VESA … #define DP_TEST_DYNAMIC_RANGE_CEA … #define DP_TEST_YCBCR_COEFFICIENTS … #define DP_YCBCR_COEFFICIENTS_ITU601 … #define DP_YCBCR_COEFFICIENTS_ITU709 … #define DP_TEST_BIT_DEPTH_MASK … #define DP_TEST_BIT_DEPTH_SHIFT … #define DP_TEST_BIT_DEPTH_6 … #define DP_TEST_BIT_DEPTH_8 … #define DP_TEST_BIT_DEPTH_10 … #define DP_TEST_BIT_DEPTH_12 … #define DP_TEST_BIT_DEPTH_16 … #define DP_TEST_MISC1 … #define DP_TEST_REFRESH_DENOMINATOR … #define DP_TEST_INTERLACED … #define DP_TEST_REFRESH_RATE_NUMERATOR … #define DP_TEST_MISC0 … #define DP_TEST_CRC_R_CR … #define DP_TEST_CRC_G_Y … #define DP_TEST_CRC_B_CB … #define DP_TEST_SINK_MISC … #define DP_TEST_CRC_SUPPORTED … #define DP_TEST_COUNT_MASK … #define DP_PHY_TEST_PATTERN … #define DP_PHY_TEST_PATTERN_SEL_MASK … #define DP_PHY_TEST_PATTERN_NONE … #define DP_PHY_TEST_PATTERN_D10_2 … #define DP_PHY_TEST_PATTERN_ERROR_COUNT … #define DP_PHY_TEST_PATTERN_PRBS7 … #define DP_PHY_TEST_PATTERN_80BIT_CUSTOM … #define DP_PHY_TEST_PATTERN_CP2520 … #define DP_PHY_SQUARE_PATTERN … #define DP_TEST_HBR2_SCRAMBLER_RESET … #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 … #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 … #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 … #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 … #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 … #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 … #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 … #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 … #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 … #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 … #define DP_TEST_RESPONSE … #define DP_TEST_ACK … #define DP_TEST_NAK … #define DP_TEST_EDID_CHECKSUM_WRITE … #define DP_TEST_EDID_CHECKSUM … #define DP_TEST_SINK … #define DP_TEST_SINK_START … #define DP_TEST_AUDIO_MODE … #define DP_TEST_AUDIO_PATTERN_TYPE … #define DP_TEST_AUDIO_PERIOD_CH1 … #define DP_TEST_AUDIO_PERIOD_CH2 … #define DP_TEST_AUDIO_PERIOD_CH3 … #define DP_TEST_AUDIO_PERIOD_CH4 … #define DP_TEST_AUDIO_PERIOD_CH5 … #define DP_TEST_AUDIO_PERIOD_CH6 … #define DP_TEST_AUDIO_PERIOD_CH7 … #define DP_TEST_AUDIO_PERIOD_CH8 … #define DP_FEC_STATUS … #define DP_FEC_DECODE_EN_DETECTED … #define DP_FEC_DECODE_DIS_DETECTED … #define DP_FEC_ERROR_COUNT_LSB … #define DP_FEC_ERROR_COUNT_MSB … #define DP_FEC_ERROR_COUNT_MASK … #define DP_FEC_ERR_COUNT_VALID … #define DP_PAYLOAD_TABLE_UPDATE_STATUS … #define DP_PAYLOAD_TABLE_UPDATED … #define DP_PAYLOAD_ACT_HANDLED … #define DP_VC_PAYLOAD_ID_SLOT_1 … /* up to ID_SLOT_63 at 0x2ff */ /* Source Device-specific */ #define DP_SOURCE_OUI … /* Sink Device-specific */ #define DP_SINK_OUI … /* Branch Device-specific */ #define DP_BRANCH_OUI … #define DP_BRANCH_ID … #define DP_BRANCH_REVISION_START … #define DP_BRANCH_HW_REV … #define DP_BRANCH_SW_REV … /* Link/Sink Device Power Control */ #define DP_SET_POWER … #define DP_SET_POWER_D0 … #define DP_SET_POWER_D3 … #define DP_SET_POWER_MASK … #define DP_SET_POWER_D3_AUX_ON … /* eDP-specific */ #define DP_EDP_DPCD_REV … #define DP_EDP_11 … #define DP_EDP_12 … #define DP_EDP_13 … #define DP_EDP_14 … #define DP_EDP_14a … #define DP_EDP_14b … #define DP_EDP_GENERAL_CAP_1 … #define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP … #define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP … #define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP … #define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP … #define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP … #define DP_EDP_FRC_ENABLE_CAP … #define DP_EDP_COLOR_ENGINE_CAP … #define DP_EDP_SET_POWER_CAP … #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP … #define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP … #define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP … #define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT … #define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP … #define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP … #define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP … #define DP_EDP_DYNAMIC_BACKLIGHT_CAP … #define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP … #define DP_EDP_GENERAL_CAP_2 … #define DP_EDP_OVERDRIVE_ENGINE_ENABLED … #define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE … #define DP_EDP_GENERAL_CAP_3 … #define DP_EDP_X_REGION_CAP_MASK … #define DP_EDP_X_REGION_CAP_SHIFT … #define DP_EDP_Y_REGION_CAP_MASK … #define DP_EDP_Y_REGION_CAP_SHIFT … #define DP_EDP_DISPLAY_CONTROL_REGISTER … #define DP_EDP_BACKLIGHT_ENABLE … #define DP_EDP_BLACK_VIDEO_ENABLE … #define DP_EDP_FRC_ENABLE … #define DP_EDP_COLOR_ENGINE_ENABLE … #define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE … #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER … #define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK … #define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM … #define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET … #define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD … #define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT … #define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE … #define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE … #define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE … #define DP_EDP_REGIONAL_BACKLIGHT_ENABLE … #define DP_EDP_UPDATE_REGION_BRIGHTNESS … #define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE … #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB … #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB … #define DP_EDP_PWMGEN_BIT_COUNT … #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN … #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX … #define DP_EDP_PWMGEN_BIT_COUNT_MASK … #define DP_EDP_BACKLIGHT_CONTROL_STATUS … #define DP_EDP_BACKLIGHT_FREQ_SET … #define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ … #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB … #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID … #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB … #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB … #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID … #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB … #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET … #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET … #define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE … #define DP_EDP_REGIONAL_BACKLIGHT_BASE … #define DP_EDP_REGIONAL_BACKLIGHT_0 … #define DP_EDP_MSO_LINK_CAPABILITIES … #define DP_EDP_MSO_NUMBER_OF_LINKS_MASK … #define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT … #define DP_EDP_MSO_INDEPENDENT_LINK_BIT … /* Sideband MSG Buffers */ #define DP_SIDEBAND_MSG_DOWN_REQ_BASE … #define DP_SIDEBAND_MSG_UP_REP_BASE … #define DP_SIDEBAND_MSG_DOWN_REP_BASE … #define DP_SIDEBAND_MSG_UP_REQ_BASE … /* DPRX Event Status Indicator */ #define DP_SINK_COUNT_ESI … #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 … #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 … #define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE … #define DP_LOCK_ACQUISITION_REQUEST … #define DP_CEC_IRQ … #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 … #define RX_CAP_CHANGED … #define LINK_STATUS_CHANGED … #define STREAM_STATUS_CHANGED … #define HDMI_LINK_STATUS_CHANGED … #define CONNECTED_OFF_ENTRY_REQUESTED … #define DP_TUNNELING_IRQ … #define DP_PSR_ERROR_STATUS … #define DP_PSR_LINK_CRC_ERROR … #define DP_PSR_RFB_STORAGE_ERROR … #define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR … #define DP_PSR_ESI … #define DP_PSR_CAPS_CHANGE … #define DP_PSR_STATUS … #define DP_PSR_SINK_INACTIVE … #define DP_PSR_SINK_ACTIVE_SRC_SYNCED … #define DP_PSR_SINK_ACTIVE_RFB … #define DP_PSR_SINK_ACTIVE_SINK_SYNCED … #define DP_PSR_SINK_ACTIVE_RESYNC … #define DP_PSR_SINK_INTERNAL_ERROR … #define DP_PSR_SINK_STATE_MASK … #define DP_SYNCHRONIZATION_LATENCY_IN_SINK … #define DP_MAX_RESYNC_FRAME_COUNT_MASK … #define DP_MAX_RESYNC_FRAME_COUNT_SHIFT … #define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK … #define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT … #define DP_LAST_RECEIVED_PSR_SDP … #define DP_PSR_STATE_BIT … #define DP_UPDATE_RFB_BIT … #define DP_CRC_VALID_BIT … #define DP_SU_VALID … #define DP_FIRST_SCAN_LINE_SU_REGION … #define DP_LAST_SCAN_LINE_SU_REGION … #define DP_Y_COORDINATE_VALID … #define DP_RECEIVER_ALPM_STATUS … #define DP_ALPM_LOCK_TIMEOUT_ERROR … #define DP_LANE0_1_STATUS_ESI … #define DP_LANE2_3_STATUS_ESI … #define DP_LANE_ALIGN_STATUS_UPDATED_ESI … #define DP_SINK_STATUS_ESI … #define DP_PANEL_REPLAY_ERROR_STATUS … #define DP_PANEL_REPLAY_LINK_CRC_ERROR … #define DP_PANEL_REPLAY_RFB_STORAGE_ERROR … #define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR … #define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS … #define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK … #define DP_SINK_FRAME_LOCKED_SHIFT … #define DP_SINK_FRAME_LOCKED_MASK … #define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT … #define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK … /* Extended Receiver Capability: See DP_DPCD_REV for definitions */ #define DP_DP13_DPCD_REV … #define DP_DPRX_FEATURE_ENUMERATION_LIST … #define DP_GTC_CAP … #define DP_SST_SPLIT_SDP_CAP … #define DP_AV_SYNC_CAP … #define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED … #define DP_VSC_EXT_VESA_SDP_SUPPORTED … #define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED … #define DP_VSC_EXT_CEA_SDP_SUPPORTED … #define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED … #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 … #define DP_ADAPTIVE_SYNC_SDP_SUPPORTED … #define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE … #define DP_ADAPTIVE_SYNC_SDP_LENGTH … #define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED … #define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED … #define DP_128B132B_SUPPORTED_LINK_RATES … #define DP_UHBR10 … #define DP_UHBR20 … #define DP_UHBR13_5 … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS … #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 … #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 … /* DSC Extended Capability Branch Total DSC Resources */ #define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT … #define DP_DSC_DECODER_COUNT_MASK … #define DP_DSC_DECODER_COUNT_SHIFT … #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 … #define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK … #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK … #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT … /* Protocol Converter Extension */ /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ #define DP_CEC_TUNNELING_CAPABILITY … #define DP_CEC_TUNNELING_CAPABLE … #define DP_CEC_SNOOPING_CAPABLE … #define DP_CEC_MULTIPLE_LA_CAPABLE … #define DP_CEC_TUNNELING_CONTROL … #define DP_CEC_TUNNELING_ENABLE … #define DP_CEC_SNOOPING_ENABLE … #define DP_CEC_RX_MESSAGE_INFO … #define DP_CEC_RX_MESSAGE_LEN_MASK … #define DP_CEC_RX_MESSAGE_LEN_SHIFT … #define DP_CEC_RX_MESSAGE_HPD_STATE … #define DP_CEC_RX_MESSAGE_HPD_LOST … #define DP_CEC_RX_MESSAGE_ACKED … #define DP_CEC_RX_MESSAGE_ENDED … #define DP_CEC_TX_MESSAGE_INFO … #define DP_CEC_TX_MESSAGE_LEN_MASK … #define DP_CEC_TX_MESSAGE_LEN_SHIFT … #define DP_CEC_TX_RETRY_COUNT_MASK … #define DP_CEC_TX_RETRY_COUNT_SHIFT … #define DP_CEC_TX_MESSAGE_SEND … #define DP_CEC_TUNNELING_IRQ_FLAGS … #define DP_CEC_RX_MESSAGE_INFO_VALID … #define DP_CEC_RX_MESSAGE_OVERFLOW … #define DP_CEC_TX_MESSAGE_SENT … #define DP_CEC_TX_LINE_ERROR … #define DP_CEC_TX_ADDRESS_NACK_ERROR … #define DP_CEC_TX_DATA_NACK_ERROR … #define DP_CEC_LOGICAL_ADDRESS_MASK … #define DP_CEC_LOGICAL_ADDRESS_0 … #define DP_CEC_LOGICAL_ADDRESS_1 … #define DP_CEC_LOGICAL_ADDRESS_2 … #define DP_CEC_LOGICAL_ADDRESS_3 … #define DP_CEC_LOGICAL_ADDRESS_4 … #define DP_CEC_LOGICAL_ADDRESS_5 … #define DP_CEC_LOGICAL_ADDRESS_6 … #define DP_CEC_LOGICAL_ADDRESS_7 … #define DP_CEC_LOGICAL_ADDRESS_MASK_2 … #define DP_CEC_LOGICAL_ADDRESS_8 … #define DP_CEC_LOGICAL_ADDRESS_9 … #define DP_CEC_LOGICAL_ADDRESS_10 … #define DP_CEC_LOGICAL_ADDRESS_11 … #define DP_CEC_LOGICAL_ADDRESS_12 … #define DP_CEC_LOGICAL_ADDRESS_13 … #define DP_CEC_LOGICAL_ADDRESS_14 … #define DP_CEC_LOGICAL_ADDRESS_15 … #define DP_CEC_RX_MESSAGE_BUFFER … #define DP_CEC_TX_MESSAGE_BUFFER … #define DP_CEC_MESSAGE_BUFFER_LENGTH … /* PCON CONFIGURE-1 FRL FOR HDMI SINK */ #define DP_PCON_HDMI_LINK_CONFIG_1 … #define DP_PCON_ENABLE_MAX_FRL_BW … #define DP_PCON_ENABLE_MAX_BW_0GBPS … #define DP_PCON_ENABLE_MAX_BW_9GBPS … #define DP_PCON_ENABLE_MAX_BW_18GBPS … #define DP_PCON_ENABLE_MAX_BW_24GBPS … #define DP_PCON_ENABLE_MAX_BW_32GBPS … #define DP_PCON_ENABLE_MAX_BW_40GBPS … #define DP_PCON_ENABLE_MAX_BW_48GBPS … #define DP_PCON_ENABLE_SOURCE_CTL_MODE … #define DP_PCON_ENABLE_CONCURRENT_LINK … #define DP_PCON_ENABLE_SEQUENTIAL_LINK … #define DP_PCON_ENABLE_LINK_FRL_MODE … #define DP_PCON_ENABLE_HPD_READY … #define DP_PCON_ENABLE_HDMI_LINK … /* PCON CONFIGURE-2 FRL FOR HDMI SINK */ #define DP_PCON_HDMI_LINK_CONFIG_2 … #define DP_PCON_MAX_LINK_BW_MASK … #define DP_PCON_FRL_BW_MASK_9GBPS … #define DP_PCON_FRL_BW_MASK_18GBPS … #define DP_PCON_FRL_BW_MASK_24GBPS … #define DP_PCON_FRL_BW_MASK_32GBPS … #define DP_PCON_FRL_BW_MASK_40GBPS … #define DP_PCON_FRL_BW_MASK_48GBPS … #define DP_PCON_FRL_LINK_TRAIN_EXTENDED … #define DP_PCON_FRL_LINK_TRAIN_NORMAL … /* PCON HDMI LINK STATUS */ #define DP_PCON_HDMI_TX_LINK_STATUS … #define DP_PCON_HDMI_TX_LINK_ACTIVE … #define DP_PCON_FRL_READY … /* PCON HDMI POST FRL STATUS */ #define DP_PCON_HDMI_POST_FRL_STATUS … #define DP_PCON_HDMI_LINK_MODE … #define DP_PCON_HDMI_MODE_TMDS … #define DP_PCON_HDMI_MODE_FRL … #define DP_PCON_HDMI_FRL_TRAINED_BW … #define DP_PCON_FRL_TRAINED_BW_9GBPS … #define DP_PCON_FRL_TRAINED_BW_18GBPS … #define DP_PCON_FRL_TRAINED_BW_24GBPS … #define DP_PCON_FRL_TRAINED_BW_32GBPS … #define DP_PCON_FRL_TRAINED_BW_40GBPS … #define DP_PCON_FRL_TRAINED_BW_48GBPS … #define DP_PROTOCOL_CONVERTER_CONTROL_0 … #define DP_HDMI_DVI_OUTPUT_CONFIG … #define DP_PROTOCOL_CONVERTER_CONTROL_1 … #define DP_CONVERSION_TO_YCBCR420_ENABLE … #define DP_HDMI_EDID_PROCESSING_DISABLE … #define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE … #define DP_HDMI_FORCE_SCRAMBLING … #define DP_PROTOCOL_CONVERTER_CONTROL_2 … #define DP_CONVERSION_TO_YCBCR422_ENABLE … #define DP_PCON_ENABLE_DSC_ENCODER … #define DP_PCON_ENCODER_PPS_OVERRIDE_MASK … #define DP_PCON_ENC_PPS_OVERRIDE_DISABLED … #define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS … #define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER … #define DP_CONVERSION_RGB_YCBCR_MASK … #define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE … #define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE … #define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE … /* PCON Downstream HDMI ERROR Status per Lane */ #define DP_PCON_HDMI_ERROR_STATUS_LN0 … #define DP_PCON_HDMI_ERROR_STATUS_LN1 … #define DP_PCON_HDMI_ERROR_STATUS_LN2 … #define DP_PCON_HDMI_ERROR_STATUS_LN3 … #define DP_PCON_HDMI_ERROR_COUNT_MASK … #define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS … #define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS … #define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS … /* PCON HDMI CONFIG PPS Override Buffer * Valid Offsets to be added to Base : 0-127 */ #define DP_PCON_HDMI_PPS_OVERRIDE_BASE … /* PCON HDMI CONFIG PPS Override Parameter: Slice height * Offset-0 8LSBs of the Slice height. * Offset-1 8MSBs of the Slice height. */ #define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT … /* PCON HDMI CONFIG PPS Override Parameter: Slice width * Offset-0 8LSBs of the Slice width. * Offset-1 8MSBs of the Slice width. */ #define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH … /* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel * Offset-0 8LSBs of the bits_per_pixel. * Offset-1 2MSBs of the bits_per_pixel. */ #define DP_PCON_HDMI_PPS_OVRD_BPP … /* HDCP 1.3 and HDCP 2.2 */ #define DP_AUX_HDCP_BKSV … #define DP_AUX_HDCP_RI_PRIME … #define DP_AUX_HDCP_AKSV … #define DP_AUX_HDCP_AN … #define DP_AUX_HDCP_V_PRIME(h) … #define DP_AUX_HDCP_BCAPS … #define DP_BCAPS_REPEATER_PRESENT … #define DP_BCAPS_HDCP_CAPABLE … #define DP_AUX_HDCP_BSTATUS … #define DP_BSTATUS_REAUTH_REQ … #define DP_BSTATUS_LINK_FAILURE … #define DP_BSTATUS_R0_PRIME_READY … #define DP_BSTATUS_READY … #define DP_AUX_HDCP_BINFO … #define DP_AUX_HDCP_KSV_FIFO … #define DP_AUX_HDCP_AINFO … /* DP HDCP2.2 parameter offsets in DPCD address space */ #define DP_HDCP_2_2_REG_RTX_OFFSET … #define DP_HDCP_2_2_REG_TXCAPS_OFFSET … #define DP_HDCP_2_2_REG_CERT_RX_OFFSET … #define DP_HDCP_2_2_REG_RRX_OFFSET … #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET … #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET … #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET … #define DP_HDCP_2_2_REG_M_OFFSET … #define DP_HDCP_2_2_REG_HPRIME_OFFSET … #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET … #define DP_HDCP_2_2_REG_RN_OFFSET … #define DP_HDCP_2_2_REG_LPRIME_OFFSET … #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET … #define DP_HDCP_2_2_REG_RIV_OFFSET … #define DP_HDCP_2_2_REG_RXINFO_OFFSET … #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET … #define DP_HDCP_2_2_REG_VPRIME_OFFSET … #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET … #define DP_HDCP_2_2_REG_V_OFFSET … #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET … #define DP_HDCP_2_2_REG_K_OFFSET … #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET … #define DP_HDCP_2_2_REG_MPRIME_OFFSET … #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET … #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET … #define DP_HDCP_2_2_REG_DBG_OFFSET … /* DP-tunneling */ #define DP_TUNNELING_OUI … #define DP_TUNNELING_OUI_BYTES … #define DP_TUNNELING_DEV_ID … #define DP_TUNNELING_DEV_ID_BYTES … #define DP_TUNNELING_HW_REV … #define DP_TUNNELING_HW_REV_MAJOR_SHIFT … #define DP_TUNNELING_HW_REV_MAJOR_MASK … #define DP_TUNNELING_HW_REV_MINOR_SHIFT … #define DP_TUNNELING_HW_REV_MINOR_MASK … #define DP_TUNNELING_SW_REV_MAJOR … #define DP_TUNNELING_SW_REV_MINOR … #define DP_TUNNELING_CAPABILITIES … #define DP_IN_BW_ALLOCATION_MODE_SUPPORT … #define DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT … #define DP_TUNNELING_SUPPORT … #define DP_IN_ADAPTER_INFO … #define DP_IN_ADAPTER_NUMBER_BITS … #define DP_IN_ADAPTER_NUMBER_MASK … #define DP_USB4_DRIVER_ID … #define DP_USB4_DRIVER_ID_BITS … #define DP_USB4_DRIVER_ID_MASK … #define DP_USB4_DRIVER_BW_CAPABILITY … #define DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT … #define DP_IN_ADAPTER_TUNNEL_INFORMATION … #define DP_GROUP_ID_BITS … #define DP_GROUP_ID_MASK … #define DP_BW_GRANULARITY … #define DP_BW_GRANULARITY_MASK … #define DP_ESTIMATED_BW … #define DP_ALLOCATED_BW … #define DP_TUNNELING_STATUS … #define DP_BW_ALLOCATION_CAPABILITY_CHANGED … #define DP_ESTIMATED_BW_CHANGED … #define DP_BW_REQUEST_SUCCEEDED … #define DP_BW_REQUEST_FAILED … #define DP_TUNNELING_MAX_LINK_RATE … #define DP_TUNNELING_MAX_LANE_COUNT … #define DP_TUNNELING_MAX_LANE_COUNT_MASK … #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL … #define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE … #define DP_UNMASK_BW_ALLOCATION_IRQ … #define DP_REQUEST_BW … #define MAX_DP_REQUEST_BW … /* LTTPR: Link Training (LT)-tunable PHY Repeaters */ #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV … #define DP_MAX_LINK_RATE_PHY_REPEATER … #define DP_PHY_REPEATER_CNT … #define DP_PHY_REPEATER_MODE … #define DP_MAX_LANE_COUNT_PHY_REPEATER … #define DP_Repeater_FEC_CAPABILITY … #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT … #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER … #define DP_PHY_REPEATER_128B132B_SUPPORTED … /* See DP_128B132B_SUPPORTED_LINK_RATES for values */ #define DP_PHY_REPEATER_128B132B_RATES … #define DP_PHY_REPEATER_EQ_DONE … enum drm_dp_phy { … }; #define DP_PHY_LTTPR(i) … #define __DP_LTTPR1_BASE … #define __DP_LTTPR2_BASE … #define DP_LTTPR_BASE(dp_phy) … #define DP_LTTPR_REG(dp_phy, lttpr1_reg) … #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 … #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) … #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 … #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) … #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 … #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 … #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 … #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 … #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) … #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 … #define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED … #define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 … #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) … /* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */ #define DP_LANE0_1_STATUS_PHY_REPEATER1 … #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) … #define DP_LANE2_3_STATUS_PHY_REPEATER1 … #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 … #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 … #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 … #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 … #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 … #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 … #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 … #define __DP_FEC1_BASE … #define __DP_FEC2_BASE … #define DP_FEC_BASE(dp_phy) … #define DP_FEC_REG(dp_phy, fec1_reg) … #define DP_FEC_STATUS_PHY_REPEATER1 … #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) … #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 … #define DP_FEC_CAPABILITY_PHY_REPEATER1 … #define DP_LTTPR_MAX_ADD … #define DP_DPCD_MAX_ADD … /* Repeater modes */ #define DP_PHY_REPEATER_MODE_TRANSPARENT … #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT … /* DP HDCP message start offsets in DPCD address space */ #define DP_HDCP_2_2_AKE_INIT_OFFSET … #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET … #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET … #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET … #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET … #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET … #define DP_HDCP_2_2_LC_INIT_OFFSET … #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET … #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET … #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET … #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET … #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET … #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET … #define HDCP_2_2_DP_RXSTATUS_LEN … #define HDCP_2_2_DP_RXSTATUS_READY(x) … #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) … #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) … #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) … #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) … /* DP 1.2 Sideband message defines */ /* peer device type - DP 1.2a Table 2-92 */ #define DP_PEER_DEVICE_NONE … #define DP_PEER_DEVICE_SOURCE_OR_SST … #define DP_PEER_DEVICE_MST_BRANCHING … #define DP_PEER_DEVICE_SST_SINK … #define DP_PEER_DEVICE_DP_LEGACY_CONV … /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ #define DP_GET_MSG_TRANSACTION_VERSION … #define DP_LINK_ADDRESS … #define DP_CONNECTION_STATUS_NOTIFY … #define DP_ENUM_PATH_RESOURCES … #define DP_ALLOCATE_PAYLOAD … #define DP_QUERY_PAYLOAD … #define DP_RESOURCE_STATUS_NOTIFY … #define DP_CLEAR_PAYLOAD_ID_TABLE … #define DP_REMOTE_DPCD_READ … #define DP_REMOTE_DPCD_WRITE … #define DP_REMOTE_I2C_READ … #define DP_REMOTE_I2C_WRITE … #define DP_POWER_UP_PHY … #define DP_POWER_DOWN_PHY … #define DP_SINK_EVENT_NOTIFY … #define DP_QUERY_STREAM_ENC_STATUS … #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST … #define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE … #define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE … /* DP 1.2 MST sideband reply types */ #define DP_SIDEBAND_REPLY_ACK … #define DP_SIDEBAND_REPLY_NAK … /* DP 1.2 MST sideband nak reasons - table 2.84 */ #define DP_NAK_WRITE_FAILURE … #define DP_NAK_INVALID_READ … #define DP_NAK_CRC_FAILURE … #define DP_NAK_BAD_PARAM … #define DP_NAK_DEFER … #define DP_NAK_LINK_FAILURE … #define DP_NAK_NO_RESOURCES … #define DP_NAK_DPCD_FAIL … #define DP_NAK_I2C_NAK … #define DP_NAK_ALLOCATE_FAIL … #define MODE_I2C_START … #define MODE_I2C_WRITE … #define MODE_I2C_READ … #define MODE_I2C_STOP … /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ #define DP_MST_PHYSICAL_PORT_0 … #define DP_MST_LOGICAL_PORT_0 … #define DP_LINK_CONSTANT_N_VALUE … #define DP_LINK_STATUS_SIZE … #define DP_BRANCH_OUI_HEADER_SIZE … #define DP_RECEIVER_CAP_SIZE … #define DP_DSC_RECEIVER_CAP_SIZE … #define EDP_PSR_RECEIVER_CAP_SIZE … #define EDP_DISPLAY_CTL_CAP_SIZE … #define DP_LTTPR_COMMON_CAP_SIZE … #define DP_LTTPR_PHY_CAP_SIZE … #define DP_SDP_AUDIO_TIMESTAMP … #define DP_SDP_AUDIO_STREAM … #define DP_SDP_EXTENSION … #define DP_SDP_AUDIO_COPYMANAGEMENT … #define DP_SDP_ISRC … #define DP_SDP_VSC … #define DP_SDP_ADAPTIVE_SYNC … #define DP_SDP_CAMERA_GENERIC(i) … #define DP_SDP_PPS … #define DP_SDP_VSC_EXT_VESA … #define DP_SDP_VSC_EXT_CEA … /* 0x80+ CEA-861 infoframe types */ #define DP_SDP_AUDIO_INFOFRAME_HB2 … /** * struct dp_sdp_header - DP secondary data packet header * @HB0: Secondary Data Packet ID * @HB1: Secondary Data Packet Type * @HB2: Secondary Data Packet Specific header, Byte 0 * @HB3: Secondary Data packet Specific header, Byte 1 */ struct dp_sdp_header { … } __packed; #define EDP_SDP_HEADER_REVISION_MASK … #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES … #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 … /** * struct dp_sdp - DP secondary data packet * @sdp_header: DP secondary data packet header * @db: DP secondaray data packet data blocks * VSC SDP Payload for PSR * db[0]: Stereo Interface * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid * db[2]: CRC value bits 7:0 of the R or Cr component * db[3]: CRC value bits 15:8 of the R or Cr component * db[4]: CRC value bits 7:0 of the G or Y component * db[5]: CRC value bits 15:8 of the G or Y component * db[6]: CRC value bits 7:0 of the B or Cb component * db[7]: CRC value bits 15:8 of the B or Cb component * db[8] - db[31]: Reserved * VSC SDP Payload for Pixel Encoding/Colorimetry Format * db[0] - db[15]: Reserved * db[16]: Pixel Encoding and Colorimetry Formats * db[17]: Dynamic Range and Component Bit Depth * db[18]: Content Type * db[19] - db[31]: Reserved */ struct dp_sdp { … } __packed; #define EDP_VSC_PSR_STATE_ACTIVE … #define EDP_VSC_PSR_UPDATE_RFB … #define EDP_VSC_PSR_CRC_VALUES_VALID … /** * enum dp_pixelformat - drm DP Pixel encoding formats * * This enum is used to indicate DP VSC SDP Pixel encoding formats. * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through * DB18] * * @DP_PIXELFORMAT_RGB: RGB pixel encoding format * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format * @DP_PIXELFORMAT_RAW: RAW pixel encoding format * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format */ enum dp_pixelformat { … }; /** * enum dp_colorimetry - drm DP Colorimetry formats * * This enum is used to indicate DP VSC SDP Colorimetry formats. * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through * DB18] and a name of enum member follows enum drm_colorimetry definition. * * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or * ITU-R BT.601 colorimetry format * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point * (scRGB (IEC 61966-2-2)) colorimetry format * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format */ enum dp_colorimetry { … }; /** * enum dp_dynamic_range - drm DP Dynamic Range * * This enum is used to indicate DP VSC SDP Dynamic Range. * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through * DB18] * * @DP_DYNAMIC_RANGE_VESA: VESA range * @DP_DYNAMIC_RANGE_CTA: CTA range */ enum dp_dynamic_range { … }; /** * enum dp_content_type - drm DP Content Type * * This enum is used to indicate DP VSC SDP Content Types. * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through * DB18] * CTA-861-G defines content types and expected processing by a sink device * * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type * @DP_CONTENT_TYPE_GRAPHICS: Graphics type * @DP_CONTENT_TYPE_PHOTO: Photo type * @DP_CONTENT_TYPE_VIDEO: Video type * @DP_CONTENT_TYPE_GAME: Game type */ enum dp_content_type { … }; enum operation_mode { … }; #endif /* _DRM_DP_H_ */
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