/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Driver for ITE Tech Inc. IT8712F/IT8512F CIR * * Copyright (C) 2010 Juan Jesús García de Soria <[email protected]> */ /* platform driver name to register */ #define ITE_DRIVER_NAME … /* FIFO sizes */ #define ITE_TX_FIFO_LEN … #define ITE_RX_FIFO_LEN … /* interrupt types */ #define ITE_IRQ_TX_FIFO … #define ITE_IRQ_RX_FIFO … #define ITE_IRQ_RX_FIFO_OVERRUN … /* forward declaration */ struct ite_dev; /* struct for storing the parameters of different recognized devices */ struct ite_dev_params { … }; /* ITE CIR device structure */ struct ite_dev { … }; /* common values for all kinds of hardware */ /* baud rate divisor default */ #define ITE_BAUDRATE_DIVISOR … /* low-speed carrier frequency limits (Hz) */ #define ITE_LCF_MIN_CARRIER_FREQ … #define ITE_LCF_MAX_CARRIER_FREQ … /* high-speed carrier frequency limits (Hz) */ #define ITE_HCF_MIN_CARRIER_FREQ … #define ITE_HCF_MAX_CARRIER_FREQ … /* default carrier freq for when demodulator is off (Hz) */ #define ITE_DEFAULT_CARRIER_FREQ … /* convert bits to us */ #define ITE_BITS_TO_US(bits, sample_period) … /* * n in RDCR produces a tolerance of +/- n * 6.25% around the center * carrier frequency... * * From two limit frequencies, L (low) and H (high), we can get both the * center frequency F = (L + H) / 2 and the variation from the center * frequency A = (H - L) / (H + L). We can use this in order to honor the * s_rx_carrier_range() call in ir-core. We'll suppose that any request * setting L=0 means we must shut down the demodulator. */ #define ITE_RXDCR_PER_10000_STEP … /* high speed carrier freq values */ #define ITE_CFQ_400 … #define ITE_CFQ_450 … #define ITE_CFQ_480 … #define ITE_CFQ_500 … /* values for pulse widths */ #define ITE_TXMPW_A … #define ITE_TXMPW_B … #define ITE_TXMPW_C … #define ITE_TXMPW_D … #define ITE_TXMPW_E … /* values for demodulator carrier range allowance */ #define ITE_RXDCR_DEFAULT … #define ITE_RXDCR_MAX … /* DR TX bits */ #define ITE_TX_PULSE … #define ITE_TX_SPACE … #define ITE_TX_MAX_RLE … #define ITE_TX_RLE_MASK … /* * IT8712F * * hardware data obtained from: * * IT8712F * Environment Control - Low Pin Count Input / Output * (EC - LPC I/O) * Preliminary Specification V0. 81 */ /* register offsets */ #define IT87_DR … #define IT87_IER … #define IT87_RCR … #define IT87_TCR1 … #define IT87_TCR2 … #define IT87_TSR … #define IT87_RSR … #define IT87_BDLR … #define IT87_BDHR … #define IT87_IIR … #define IT87_IOREG_LENGTH … /* IER bits */ #define IT87_TLDLIE … #define IT87_RDAIE … #define IT87_RFOIE … #define IT87_IEC … #define IT87_BR … #define IT87_RESET … /* RCR bits */ #define IT87_RXDCR … #define IT87_RXACT … #define IT87_RXEND … #define IT87_RXEN … #define IT87_HCFS … #define IT87_RDWOS … /* TCR1 bits */ #define IT87_TXMPM … #define IT87_TXMPM_DEFAULT … #define IT87_TXENDF … #define IT87_TXRLE … #define IT87_FIFOTL … #define IT87_FIFOTL_DEFAULT … #define IT87_ILE … #define IT87_FIFOCLR … /* TCR2 bits */ #define IT87_TXMPW … #define IT87_TXMPW_DEFAULT … #define IT87_CFQ … #define IT87_CFQ_SHIFT … /* TSR bits */ #define IT87_TXFBC … /* RSR bits */ #define IT87_RXFBC … #define IT87_RXFTO … /* IIR bits */ #define IT87_IP … #define IT87_II … #define IT87_II_NOINT … #define IT87_II_TXLDL … #define IT87_II_RXDS … #define IT87_II_RXFO … /* * IT8512E/F * * Hardware data obtained from: * * IT8512E/F * Embedded Controller * Preliminary Specification V0.4.1 * * Note that the CIR registers are not directly available to the host, because * they only are accessible to the integrated microcontroller. Thus, in order * use it, some kind of bridging is required. As the bridging may depend on * the controller firmware in use, we are going to use the PNP ID in order to * determine the strategy and ports available. See after these generic * IT8512E/F register definitions for register definitions for those * strategies. */ /* register offsets */ #define IT85_C0DR … #define IT85_C0MSTCR … #define IT85_C0IER … #define IT85_C0IIR … #define IT85_C0CFR … #define IT85_C0RCR … #define IT85_C0TCR … #define IT85_C0SCK … #define IT85_C0BDLR … #define IT85_C0BDHR … #define IT85_C0TFSR … #define IT85_C0RFSR … #define IT85_C0WCL … #define IT85_C0WCR … #define IT85_C0WPS … #define IT85_IOREG_LENGTH … /* C0MSTCR bits */ #define IT85_RESET … #define IT85_FIFOCLR … #define IT85_FIFOTL … #define IT85_FIFOTL_DEFAULT … #define IT85_ILE … #define IT85_ILSEL … /* C0IER bits */ #define IT85_TLDLIE … #define IT85_RDAIE … #define IT85_RFOIE … #define IT85_IEC … /* C0IIR bits */ #define IT85_TLDLI … #define IT85_RDAI … #define IT85_RFOI … #define IT85_NIP … /* C0CFR bits */ #define IT85_CFQ … #define IT85_HCFS … /* C0RCR bits */ #define IT85_RXDCR … #define IT85_RXACT … #define IT85_RXEND … #define IT85_RDWOS … #define IT85_RXEN … /* C0TCR bits */ #define IT85_TXMPW … #define IT85_TXMPW_DEFAULT … #define IT85_TXMPM … #define IT85_TXMPM_DEFAULT … #define IT85_TXENDF … #define IT85_TXRLE … /* C0SCK bits */ #define IT85_SCKS … #define IT85_TXDCKG … #define IT85_DLL1P8E … #define IT85_DLLTE … #define IT85_BRCM … #define IT85_DLLOCK … /* C0TFSR bits */ #define IT85_TXFBC … /* C0RFSR bits */ #define IT85_RXFBC … #define IT85_RXFTO … /* C0WCL bits */ #define IT85_WCL … /* C0WPS bits */ #define IT85_CIRPOSIE … #define IT85_CIRPOIS … #define IT85_CIRPOII … #define IT85_RCRST … #define IT85_WCRST … /* * ITE8708 * * Hardware data obtained from hacked driver for IT8512 in this forum post: * * http://ubuntuforums.org/showthread.php?t=1028640 * * Although there's no official documentation for that driver, analysis would * suggest that it maps the 16 registers of IT8512 onto two 8-register banks, * selectable by a single bank-select bit that's mapped onto both banks. The * IT8512 registers are mapped in a different order, so that the first bank * maps the ones that are used more often, and two registers that share a * reserved high-order bit are placed at the same offset in both banks in * order to reuse the reserved bit as the bank select bit. */ /* register offsets */ /* mapped onto both banks */ #define IT8708_BANKSEL … #define IT8708_HRAE … /* mapped onto the low bank */ #define IT8708_C0DR … #define IT8708_C0MSTCR … #define IT8708_C0IER … #define IT8708_C0IIR … #define IT8708_C0RFSR … #define IT8708_C0RCR … #define IT8708_C0TFSR … #define IT8708_C0TCR … /* mapped onto the high bank */ #define IT8708_C0BDLR … #define IT8708_C0BDHR … #define IT8708_C0CFR … /* registers whose bank mapping we don't know, since they weren't being used * in the hacked driver... most probably they belong to the high bank too, * since they fit in the holes the other registers leave */ #define IT8708_C0SCK … #define IT8708_C0WCL … #define IT8708_C0WCR … #define IT8708_C0WPS … #define IT8708_IOREG_LENGTH … /* two more registers that are defined in the hacked driver, but can't be * found in the data sheets; no idea what they are or how they are accessed, * since the hacked driver doesn't seem to use them */ #define IT8708_CSCRR … #define IT8708_CGPINTR … /* CSCRR bits */ #define IT8708_CSCRR_SCRB … #define IT8708_CSCRR_PM … /* CGPINTR bits */ #define IT8708_CGPINT … /* * ITE8709 * * Hardware interfacing data obtained from the original lirc_ite8709 driver. * Verbatim from its sources: * * The ITE8709 device seems to be the combination of IT8512 superIO chip and * a specific firmware running on the IT8512's embedded micro-controller. * In addition of the embedded micro-controller, the IT8512 chip contains a * CIR module and several other modules. A few modules are directly accessible * by the host CPU, but most of them are only accessible by the * micro-controller. The CIR module is only accessible by the * micro-controller. * * The battery-backed SRAM module is accessible by the host CPU and the * micro-controller. So one of the MC's firmware role is to act as a bridge * between the host CPU and the CIR module. The firmware implements a kind of * communication protocol using the SRAM module as a shared memory. The IT8512 * specification is publicly available on ITE's web site, but the * communication protocol is not, so it was reverse-engineered. */ /* register offsets */ #define IT8709_RAM_IDX … #define IT8709_RAM_VAL … #define IT8709_IOREG_LENGTH … /* register offsets inside the SRAM module */ #define IT8709_MODE … #define IT8709_REG_IDX … #define IT8709_REG_VAL … #define IT8709_IIR … #define IT8709_RFSR … #define IT8709_FIFO … /* MODE values */ #define IT8709_IDLE … #define IT8709_WRITE … #define IT8709_READ …
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