/* * Driver for Amlogic Meson AO CEC Controller * * Copyright (C) 2015 Amlogic, Inc. All rights reserved * Copyright (C) 2017 BayLibre, SAS * Author: Neil Armstrong <[email protected]> * * SPDX-License-Identifier: GPL-2.0+ */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/device.h> #include <linux/io.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/types.h> #include <linux/interrupt.h> #include <linux/reset.h> #include <media/cec.h> #include <media/cec-notifier.h> /* CEC Registers */ /* * [2:1] cntl_clk * - 0 = Disable clk (Power-off mode) * - 1 = Enable gated clock (Normal mode) * - 2 = Enable free-run clk (Debug mode) */ #define CEC_GEN_CNTL_REG … #define CEC_GEN_CNTL_RESET … #define CEC_GEN_CNTL_CLK_DISABLE … #define CEC_GEN_CNTL_CLK_ENABLE … #define CEC_GEN_CNTL_CLK_ENABLE_DBG … #define CEC_GEN_CNTL_CLK_CTRL_MASK … /* * [7:0] cec_reg_addr * [15:8] cec_reg_wrdata * [16] cec_reg_wr * - 0 = Read * - 1 = Write * [23] bus free * [31:24] cec_reg_rddata */ #define CEC_RW_REG … #define CEC_RW_ADDR … #define CEC_RW_WR_DATA … #define CEC_RW_WRITE_EN … #define CEC_RW_BUS_BUSY … #define CEC_RW_RD_DATA … /* * [1] tx intr * [2] rx intr */ #define CEC_INTR_MASKN_REG … #define CEC_INTR_CLR_REG … #define CEC_INTR_STAT_REG … #define CEC_INTR_TX … #define CEC_INTR_RX … /* CEC Commands */ #define CEC_TX_MSG_0_HEADER … #define CEC_TX_MSG_1_OPCODE … #define CEC_TX_MSG_2_OP1 … #define CEC_TX_MSG_3_OP2 … #define CEC_TX_MSG_4_OP3 … #define CEC_TX_MSG_5_OP4 … #define CEC_TX_MSG_6_OP5 … #define CEC_TX_MSG_7_OP6 … #define CEC_TX_MSG_8_OP7 … #define CEC_TX_MSG_9_OP8 … #define CEC_TX_MSG_A_OP9 … #define CEC_TX_MSG_B_OP10 … #define CEC_TX_MSG_C_OP11 … #define CEC_TX_MSG_D_OP12 … #define CEC_TX_MSG_E_OP13 … #define CEC_TX_MSG_F_OP14 … #define CEC_TX_MSG_LENGTH … #define CEC_TX_MSG_CMD … #define CEC_TX_WRITE_BUF … #define CEC_TX_CLEAR_BUF … #define CEC_RX_MSG_CMD … #define CEC_RX_CLEAR_BUF … #define CEC_LOGICAL_ADDR0 … #define CEC_LOGICAL_ADDR1 … #define CEC_LOGICAL_ADDR2 … #define CEC_LOGICAL_ADDR3 … #define CEC_LOGICAL_ADDR4 … #define CEC_CLOCK_DIV_H … #define CEC_CLOCK_DIV_L … #define CEC_QUIESCENT_25MS_BIT7_0 … #define CEC_QUIESCENT_25MS_BIT11_8 … #define CEC_STARTBITMINL2H_3MS5_BIT7_0 … #define CEC_STARTBITMINL2H_3MS5_BIT8 … #define CEC_STARTBITMAXL2H_3MS9_BIT7_0 … #define CEC_STARTBITMAXL2H_3MS9_BIT8 … #define CEC_STARTBITMINH_0MS6_BIT7_0 … #define CEC_STARTBITMINH_0MS6_BIT8 … #define CEC_STARTBITMAXH_1MS0_BIT7_0 … #define CEC_STARTBITMAXH_1MS0_BIT8 … #define CEC_STARTBITMINTOT_4MS3_BIT7_0 … #define CEC_STARTBITMINTOT_4MS3_BIT9_8 … #define CEC_STARTBITMAXTOT_4MS7_BIT7_0 … #define CEC_STARTBITMAXTOT_4MS7_BIT9_8 … #define CEC_LOGIC1MINL2H_0MS4_BIT7_0 … #define CEC_LOGIC1MINL2H_0MS4_BIT8 … #define CEC_LOGIC1MAXL2H_0MS8_BIT7_0 … #define CEC_LOGIC1MAXL2H_0MS8_BIT8 … #define CEC_LOGIC0MINL2H_1MS3_BIT7_0 … #define CEC_LOGIC0MINL2H_1MS3_BIT8 … #define CEC_LOGIC0MAXL2H_1MS7_BIT7_0 … #define CEC_LOGIC0MAXL2H_1MS7_BIT8 … #define CEC_LOGICMINTOTAL_2MS05_BIT7_0 … #define CEC_LOGICMINTOTAL_2MS05_BIT9_8 … #define CEC_LOGICMAXHIGH_2MS8_BIT7_0 … #define CEC_LOGICMAXHIGH_2MS8_BIT8 … #define CEC_LOGICERRLOW_3MS4_BIT7_0 … #define CEC_LOGICERRLOW_3MS4_BIT8 … #define CEC_NOMSMPPOINT_1MS05 … #define CEC_DELCNTR_LOGICERR … #define CEC_TXTIME_17MS_BIT7_0 … #define CEC_TXTIME_17MS_BIT10_8 … #define CEC_TXTIME_2BIT_BIT7_0 … #define CEC_TXTIME_2BIT_BIT10_8 … #define CEC_TXTIME_4BIT_BIT7_0 … #define CEC_TXTIME_4BIT_BIT10_8 … #define CEC_STARTBITNOML2H_3MS7_BIT7_0 … #define CEC_STARTBITNOML2H_3MS7_BIT8 … #define CEC_STARTBITNOMH_0MS8_BIT7_0 … #define CEC_STARTBITNOMH_0MS8_BIT8 … #define CEC_LOGIC1NOML2H_0MS6_BIT7_0 … #define CEC_LOGIC1NOML2H_0MS6_BIT8 … #define CEC_LOGIC0NOML2H_1MS5_BIT7_0 … #define CEC_LOGIC0NOML2H_1MS5_BIT8 … #define CEC_LOGIC1NOMH_1MS8_BIT7_0 … #define CEC_LOGIC1NOMH_1MS8_BIT8 … #define CEC_LOGIC0NOMH_0MS9_BIT7_0 … #define CEC_LOGIC0NOMH_0MS9_BIT8 … #define CEC_LOGICERRLOW_3MS6_BIT7_0 … #define CEC_LOGICERRLOW_3MS6_BIT8 … #define CEC_CHKCONTENTION_0MS1 … #define CEC_PREPARENXTBIT_0MS05_BIT7_0 … #define CEC_PREPARENXTBIT_0MS05_BIT8 … #define CEC_NOMSMPACKPOINT_0MS45 … #define CEC_ACK0NOML2H_1MS5_BIT7_0 … #define CEC_ACK0NOML2H_1MS5_BIT8 … #define CEC_BUGFIX_DISABLE_0 … #define CEC_BUGFIX_DISABLE_1 … #define CEC_RX_MSG_0_HEADER … #define CEC_RX_MSG_1_OPCODE … #define CEC_RX_MSG_2_OP1 … #define CEC_RX_MSG_3_OP2 … #define CEC_RX_MSG_4_OP3 … #define CEC_RX_MSG_5_OP4 … #define CEC_RX_MSG_6_OP5 … #define CEC_RX_MSG_7_OP6 … #define CEC_RX_MSG_8_OP7 … #define CEC_RX_MSG_9_OP8 … #define CEC_RX_MSG_A_OP9 … #define CEC_RX_MSG_B_OP10 … #define CEC_RX_MSG_C_OP11 … #define CEC_RX_MSG_D_OP12 … #define CEC_RX_MSG_E_OP13 … #define CEC_RX_MSG_F_OP14 … #define CEC_RX_MSG_LENGTH … #define CEC_RX_MSG_STATUS … #define CEC_RX_NUM_MSG … #define CEC_TX_MSG_STATUS … #define CEC_TX_NUM_MSG … /* CEC_TX_MSG_CMD definition */ #define TX_NO_OP … #define TX_REQ_CURRENT … #define TX_ABORT … #define TX_REQ_NEXT … /* tx_msg_status definition */ #define TX_IDLE … #define TX_BUSY … #define TX_DONE … #define TX_ERROR … /* rx_msg_cmd */ #define RX_NO_OP … #define RX_ACK_CURRENT … #define RX_DISABLE … #define RX_ACK_NEXT … /* rx_msg_status */ #define RX_IDLE … #define RX_BUSY … #define RX_DONE … #define RX_ERROR … /* RX_CLEAR_BUF options */ #define CLEAR_START … #define CLEAR_STOP … /* CEC_LOGICAL_ADDRx options */ #define LOGICAL_ADDR_MASK … #define LOGICAL_ADDR_VALID … #define LOGICAL_ADDR_DISABLE … #define CEC_CLK_RATE … struct meson_ao_cec_device { … }; #define writel_bits_relaxed(mask, val, addr) … static inline int meson_ao_cec_wait_busy(struct meson_ao_cec_device *ao_cec) { … } static void meson_ao_cec_read(struct meson_ao_cec_device *ao_cec, unsigned long address, u8 *data, int *res) { … } static void meson_ao_cec_write(struct meson_ao_cec_device *ao_cec, unsigned long address, u8 data, int *res) { … } static inline void meson_ao_cec_irq_setup(struct meson_ao_cec_device *ao_cec, bool enable) { … } static inline int meson_ao_cec_clear(struct meson_ao_cec_device *ao_cec) { … } static int meson_ao_cec_arbit_bit_time_set(struct meson_ao_cec_device *ao_cec, unsigned int bit_set, unsigned int time_set) { … } static irqreturn_t meson_ao_cec_irq(int irq, void *data) { … } static void meson_ao_cec_irq_tx(struct meson_ao_cec_device *ao_cec) { … } static void meson_ao_cec_irq_rx(struct meson_ao_cec_device *ao_cec) { … } static irqreturn_t meson_ao_cec_irq_thread(int irq, void *data) { … } static int meson_ao_cec_set_log_addr(struct cec_adapter *adap, u8 logical_addr) { … } static int meson_ao_cec_transmit(struct cec_adapter *adap, u8 attempts, u32 signal_free_time, struct cec_msg *msg) { … } static int meson_ao_cec_adap_enable(struct cec_adapter *adap, bool enable) { … } static const struct cec_adap_ops meson_ao_cec_ops = …; static int meson_ao_cec_probe(struct platform_device *pdev) { … } static void meson_ao_cec_remove(struct platform_device *pdev) { … } static const struct of_device_id meson_ao_cec_of_match[] = …; MODULE_DEVICE_TABLE(of, meson_ao_cec_of_match); static struct platform_driver meson_ao_cec_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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