// SPDX-License-Identifier: GPL-2.0+ /* * Driver for Amlogic Meson AO CEC G12A Controller * * Copyright (C) 2017 Amlogic, Inc. All rights reserved * Copyright (C) 2019 BayLibre, SAS * Author: Neil Armstrong <[email protected]> */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/device.h> #include <linux/io.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/types.h> #include <linux/interrupt.h> #include <linux/reset.h> #include <linux/slab.h> #include <linux/regmap.h> #include <media/cec.h> #include <media/cec-notifier.h> #include <linux/clk-provider.h> /* CEC Registers */ #define CECB_CLK_CNTL_REG0 … #define CECB_CLK_CNTL_N1 … #define CECB_CLK_CNTL_N2 … #define CECB_CLK_CNTL_DUAL_EN … #define CECB_CLK_CNTL_OUTPUT_EN … #define CECB_CLK_CNTL_INPUT_EN … #define CECB_CLK_CNTL_REG1 … #define CECB_CLK_CNTL_M1 … #define CECB_CLK_CNTL_M2 … #define CECB_CLK_CNTL_BYPASS_EN … /* * [14:12] Filter_del. For glitch-filtering CEC line, ignore signal * change pulse width < filter_del * T(filter_tick) * 3. * [9:8] Filter_tick_sel: Select which periodical pulse for * glitch-filtering CEC line signal. * - 0=Use T(xtal)*3 = 125ns; * - 1=Use once-per-1us pulse; * - 2=Use once-per-10us pulse; * - 3=Use once-per-100us pulse. * [3] Sysclk_en. 0=Disable system clock; 1=Enable system clock. * [2:1] cntl_clk * - 0 = Disable clk (Power-off mode) * - 1 = Enable gated clock (Normal mode) * - 2 = Enable free-run clk (Debug mode) * [0] SW_RESET 1=Apply reset; 0=No reset. */ #define CECB_GEN_CNTL_REG … #define CECB_GEN_CNTL_RESET … #define CECB_GEN_CNTL_CLK_DISABLE … #define CECB_GEN_CNTL_CLK_ENABLE … #define CECB_GEN_CNTL_CLK_ENABLE_DBG … #define CECB_GEN_CNTL_CLK_CTRL_MASK … #define CECB_GEN_CNTL_SYS_CLK_EN … #define CECB_GEN_CNTL_FILTER_TICK_125NS … #define CECB_GEN_CNTL_FILTER_TICK_1US … #define CECB_GEN_CNTL_FILTER_TICK_10US … #define CECB_GEN_CNTL_FILTER_TICK_100US … #define CECB_GEN_CNTL_FILTER_TICK_SEL … #define CECB_GEN_CNTL_FILTER_DEL … /* * [7:0] cec_reg_addr * [15:8] cec_reg_wrdata * [16] cec_reg_wr * - 0 = Read * - 1 = Write * [31:24] cec_reg_rddata */ #define CECB_RW_REG … #define CECB_RW_ADDR … #define CECB_RW_WR_DATA … #define CECB_RW_WRITE_EN … #define CECB_RW_BUS_BUSY … #define CECB_RW_RD_DATA … /* * [0] DONE Interrupt * [1] End Of Message Interrupt * [2] Not Acknowlegde Interrupt * [3] Arbitration Loss Interrupt * [4] Initiator Error Interrupt * [5] Follower Error Interrupt * [6] Wake-Up Interrupt */ #define CECB_INTR_MASKN_REG … #define CECB_INTR_CLR_REG … #define CECB_INTR_STAT_REG … #define CECB_INTR_DONE … #define CECB_INTR_EOM … #define CECB_INTR_NACK … #define CECB_INTR_ARB_LOSS … #define CECB_INTR_INITIATOR_ERR … #define CECB_INTR_FOLLOWER_ERR … #define CECB_INTR_WAKE_UP … /* CEC Commands */ #define CECB_CTRL … #define CECB_CTRL_SEND … #define CECB_CTRL_TYPE … #define CECB_CTRL_TYPE_RETRY … #define CECB_CTRL_TYPE_NEW … #define CECB_CTRL_TYPE_NEXT … #define CECB_CTRL2 … #define CECB_CTRL2_RISE_DEL_MAX … #define CECB_INTR_MASK … #define CECB_LADD_LOW … #define CECB_LADD_HIGH … #define CECB_TX_CNT … #define CECB_RX_CNT … #define CECB_STAT0 … #define CECB_TX_DATA00 … #define CECB_TX_DATA01 … #define CECB_TX_DATA02 … #define CECB_TX_DATA03 … #define CECB_TX_DATA04 … #define CECB_TX_DATA05 … #define CECB_TX_DATA06 … #define CECB_TX_DATA07 … #define CECB_TX_DATA08 … #define CECB_TX_DATA09 … #define CECB_TX_DATA10 … #define CECB_TX_DATA11 … #define CECB_TX_DATA12 … #define CECB_TX_DATA13 … #define CECB_TX_DATA14 … #define CECB_TX_DATA15 … #define CECB_RX_DATA00 … #define CECB_RX_DATA01 … #define CECB_RX_DATA02 … #define CECB_RX_DATA03 … #define CECB_RX_DATA04 … #define CECB_RX_DATA05 … #define CECB_RX_DATA06 … #define CECB_RX_DATA07 … #define CECB_RX_DATA08 … #define CECB_RX_DATA09 … #define CECB_RX_DATA10 … #define CECB_RX_DATA11 … #define CECB_RX_DATA12 … #define CECB_RX_DATA13 … #define CECB_RX_DATA14 … #define CECB_RX_DATA15 … #define CECB_LOCK_BUF … #define CECB_LOCK_BUF_EN … #define CECB_WAKEUPCTRL … struct meson_ao_cec_g12a_data { … }; struct meson_ao_cec_g12a_device { … }; static const struct regmap_config meson_ao_cec_g12a_regmap_conf = …; /* * The AO-CECB embeds a dual/divider to generate a more precise * 32,768KHz clock for CEC core clock. * ______ ______ * | | | | * ______ | Div1 |-| Cnt1 | ______ * | | /|______| |______|\ | | * Xtal-->| Gate |---| ______ ______ X-X--| Gate |--> * |______| | \| | | |/ | |______| * | | Div2 |-| Cnt2 | | * | |______| |______| | * |_______________________| * * The dividing can be switched to single or dual, with a counter * for each divider to set when the switching is done. * The entire dividing mechanism can be also bypassed. */ struct meson_ao_cec_g12a_dualdiv_clk { … }; #define hw_to_meson_ao_cec_g12a_dualdiv_clk(_hw) … \ static unsigned long meson_ao_cec_g12a_dualdiv_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int meson_ao_cec_g12a_dualdiv_clk_enable(struct clk_hw *hw) { … } static void meson_ao_cec_g12a_dualdiv_clk_disable(struct clk_hw *hw) { … } static int meson_ao_cec_g12a_dualdiv_clk_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops meson_ao_cec_g12a_dualdiv_clk_ops = …; static int meson_ao_cec_g12a_setup_clk(struct meson_ao_cec_g12a_device *ao_cec) { … } static int meson_ao_cec_g12a_read(void *context, unsigned int addr, unsigned int *data) { … } static int meson_ao_cec_g12a_write(void *context, unsigned int addr, unsigned int data) { … } static const struct regmap_config meson_ao_cec_g12a_cec_regmap_conf = …; static inline void meson_ao_cec_g12a_irq_setup(struct meson_ao_cec_g12a_device *ao_cec, bool enable) { … } static void meson_ao_cec_g12a_irq_rx(struct meson_ao_cec_g12a_device *ao_cec) { … } static irqreturn_t meson_ao_cec_g12a_irq(int irq, void *data) { … } static irqreturn_t meson_ao_cec_g12a_irq_thread(int irq, void *data) { … } static int meson_ao_cec_g12a_set_log_addr(struct cec_adapter *adap, u8 logical_addr) { … } static int meson_ao_cec_g12a_transmit(struct cec_adapter *adap, u8 attempts, u32 signal_free_time, struct cec_msg *msg) { … } static int meson_ao_cec_g12a_adap_enable(struct cec_adapter *adap, bool enable) { … } static const struct cec_adap_ops meson_ao_cec_g12a_ops = …; static int meson_ao_cec_g12a_probe(struct platform_device *pdev) { … } static void meson_ao_cec_g12a_remove(struct platform_device *pdev) { … } static const struct meson_ao_cec_g12a_data ao_cec_g12a_data = …; static const struct meson_ao_cec_g12a_data ao_cec_sm1_data = …; static const struct of_device_id meson_ao_cec_g12a_of_match[] = …; MODULE_DEVICE_TABLE(of, meson_ao_cec_g12a_of_match); static struct platform_driver meson_ao_cec_g12a_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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