/* SPDX-License-Identifier: GPL-2.0-only */ /* * Tegra CEC register definitions * * The original 3.10 CEC driver using a custom API: * * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved. * * Conversion to the CEC framework and to the mainline kernel: * * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved. */ #ifndef TEGRA_CEC_H #define TEGRA_CEC_H /* CEC registers */ #define TEGRA_CEC_SW_CONTROL … #define TEGRA_CEC_HW_CONTROL … #define TEGRA_CEC_INPUT_FILTER … #define TEGRA_CEC_TX_REGISTER … #define TEGRA_CEC_RX_REGISTER … #define TEGRA_CEC_RX_TIMING_0 … #define TEGRA_CEC_RX_TIMING_1 … #define TEGRA_CEC_RX_TIMING_2 … #define TEGRA_CEC_TX_TIMING_0 … #define TEGRA_CEC_TX_TIMING_1 … #define TEGRA_CEC_TX_TIMING_2 … #define TEGRA_CEC_INT_STAT … #define TEGRA_CEC_INT_MASK … #define TEGRA_CEC_HW_DEBUG_RX … #define TEGRA_CEC_HW_DEBUG_TX … #define TEGRA_CEC_HWCTRL_RX_LADDR_MASK … #define TEGRA_CEC_HWCTRL_RX_LADDR(x) … #define TEGRA_CEC_HWCTRL_RX_SNOOP … #define TEGRA_CEC_HWCTRL_RX_NAK_MODE … #define TEGRA_CEC_HWCTRL_TX_NAK_MODE … #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE … #define TEGRA_CEC_HWCTRL_TX_RX_MODE … #define TEGRA_CEC_INPUT_FILTER_MODE … #define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT … #define TEGRA_CEC_TX_REG_DATA_SHIFT … #define TEGRA_CEC_TX_REG_EOM … #define TEGRA_CEC_TX_REG_BCAST … #define TEGRA_CEC_TX_REG_START_BIT … #define TEGRA_CEC_TX_REG_RETRY … #define TEGRA_CEC_RX_REGISTER_SHIFT … #define TEGRA_CEC_RX_REGISTER_EOM … #define TEGRA_CEC_RX_REGISTER_ACK … #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT … #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT … #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT … #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT … #define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT … #define TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT … #define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT … #define TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT … #define TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT … #define TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT … #define TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT … #define TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT … #define TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT … #define TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT … #define TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT … #define TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT … #define TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT … #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT … #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT … #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT … #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY … #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN … #define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD … #define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED … #define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED … #define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED … #define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL … #define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN … #define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED … #define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED … #define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED … #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L … #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H … #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY … #define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN … #define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD … #define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED … #define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED … #define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED … #define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL … #define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN … #define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED … #define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED … #define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED … #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L … #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H … #define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT … #define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT … #define TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT … #define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT … #define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER … #endif /* TEGRA_CEC_H */
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