/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * SECO X86 Boards CEC register defines * * Author: Ettore Chimenti <[email protected]> * Copyright (C) 2018, SECO Spa. * Copyright (C) 2018, Aidilab Srl. */ #ifndef __SECO_CEC_H__ #define __SECO_CEC_H__ #define SECOCEC_MAX_ADDRS … #define SECOCEC_DEV_NAME … #define SECOCEC_LATEST_FW … #define SMBTIMEOUT … #define SMB_POLL_UDELAY … #define SMBUS_WRITE … #define SMBUS_READ … #define CMD_BYTE_DATA … #define CMD_WORD_DATA … /* * SMBus definitons for Braswell */ #define BRA_DONE_STATUS … #define BRA_INUSE_STS … #define BRA_FAILED_OP … #define BRA_BUS_ERR … #define BRA_DEV_ERR … #define BRA_INTR … #define BRA_HOST_BUSY … #define BRA_HSTS_ERR_MASK … #define BRA_PEC_EN … #define BRA_START … #define BRA_LAST__BYTE … #define BRA_INTREN … #define BRA_SMB_CMD … #define BRA_SMB_CMD_QUICK … #define BRA_SMB_CMD_BYTE … #define BRA_SMB_CMD_BYTE_DATA … #define BRA_SMB_CMD_WORD_DATA … #define BRA_SMB_CMD_PROCESS_CALL … #define BRA_SMB_CMD_BLOCK … #define BRA_SMB_CMD_I2CREAD … #define BRA_SMB_CMD_BLOCK_PROCESS … #define BRA_SMB_BASE_ADDR … #define HSTS … #define HCNT … #define HCMD … #define XMIT_SLVA … #define HDAT0 … #define HDAT1 … /* * Microcontroller Address */ #define SECOCEC_MICRO_ADDRESS … /* * STM32 SMBus Registers */ #define SECOCEC_VERSION … #define SECOCEC_ENABLE_REG_1 … #define SECOCEC_ENABLE_REG_2 … #define SECOCEC_STATUS_REG_1 … #define SECOCEC_STATUS_REG_2 … #define SECOCEC_STATUS … #define SECOCEC_DEVICE_LA … #define SECOCEC_READ_OPERATION_ID … #define SECOCEC_READ_DATA_LENGTH … #define SECOCEC_READ_DATA_00 … #define SECOCEC_READ_DATA_02 … #define SECOCEC_READ_DATA_04 … #define SECOCEC_READ_DATA_06 … #define SECOCEC_READ_DATA_08 … #define SECOCEC_READ_DATA_10 … #define SECOCEC_READ_DATA_12 … #define SECOCEC_READ_BYTE0 … #define SECOCEC_WRITE_OPERATION_ID … #define SECOCEC_WRITE_DATA_LENGTH … #define SECOCEC_WRITE_DATA_00 … #define SECOCEC_WRITE_DATA_02 … #define SECOCEC_WRITE_DATA_04 … #define SECOCEC_WRITE_DATA_06 … #define SECOCEC_WRITE_DATA_08 … #define SECOCEC_WRITE_DATA_10 … #define SECOCEC_WRITE_DATA_12 … #define SECOCEC_WRITE_BYTE0 … #define SECOCEC_IR_READ_DATA … /* * IR */ #define SECOCEC_IR_COMMAND_MASK … #define SECOCEC_IR_COMMAND_SHL … #define SECOCEC_IR_ADDRESS_MASK … #define SECOCEC_IR_ADDRESS_SHL … #define SECOCEC_IR_TOGGLE_MASK … #define SECOCEC_IR_TOGGLE_SHL … /* * Enabling register */ #define SECOCEC_ENABLE_REG_1_CEC … #define SECOCEC_ENABLE_REG_1_IR … #define SECOCEC_ENABLE_REG_1_IR_PASSTHROUGH … /* * Status register */ #define SECOCEC_STATUS_REG_1_CEC … #define SECOCEC_STATUS_REG_1_IR … #define SECOCEC_STATUS_REG_1_IR_PASSTHR … /* * Status data */ #define SECOCEC_STATUS_MSG_RECEIVED_MASK … #define SECOCEC_STATUS_RX_ERROR_MASK … #define SECOCEC_STATUS_MSG_SENT_MASK … #define SECOCEC_STATUS_TX_ERROR_MASK … #define SECOCEC_STATUS_TX_NACK_ERROR … #define SECOCEC_STATUS_RX_OVERFLOW_MASK … #endif /* __SECO_CEC_H__ */
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