/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __SAA7146__ #define __SAA7146__ #include <linux/delay.h> /* for delay-stuff */ #include <linux/slab.h> /* for kmalloc/kfree */ #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */ #include <linux/init.h> /* for "__init" */ #include <linux/interrupt.h> /* for IMMEDIATE_BH */ #include <linux/kmod.h> /* for kernel module loader */ #include <linux/i2c.h> /* for i2c subsystem */ #include <asm/io.h> /* for accessing devices */ #include <linux/stringify.h> #include <linux/mutex.h> #include <linux/scatterlist.h> #include <media/v4l2-device.h> #include <media/v4l2-ctrls.h> #include <linux/vmalloc.h> /* for vmalloc() */ #include <linux/mm.h> /* for vmalloc_to_page() */ #define saa7146_write(sxy,adr,dat) … #define saa7146_read(sxy,adr) … extern unsigned int saa7146_debug; #ifndef DEBUG_VARIABLE #define DEBUG_VARIABLE … #endif #define ERR(fmt, ...) … #define _DBG(mask, fmt, ...) … /* simple debug messages */ #define DEB_S(fmt, ...) … /* more detailed debug messages */ #define DEB_D(fmt, ...) … /* print enter and exit of functions */ #define DEB_EE(fmt, ...) … /* i2c debug messages */ #define DEB_I2C(fmt, ...) … /* vbi debug messages */ #define DEB_VBI(fmt, ...) … /* interrupt debug messages */ #define DEB_INT(fmt, ...) … /* capture debug messages */ #define DEB_CAP(fmt, ...) … #define SAA7146_ISR_CLEAR(x,y) … struct module; struct saa7146_dev; struct saa7146_extension; struct saa7146_vv; /* saa7146 page table */ struct saa7146_pgtable { … }; struct saa7146_pci_extension_data { … }; #define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) … struct saa7146_extension { … }; struct saa7146_dma { … }; struct saa7146_dev { … }; static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev) { … } /* from saa7146_i2c.c */ int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); /* from saa7146_core.c */ int saa7146_register_extension(struct saa7146_extension*); int saa7146_unregister_extension(struct saa7146_extension*); struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc); int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt); void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt); int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length ); void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt); void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data); int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop); /* some memory sizes */ #define SAA7146_I2C_MEM … #define SAA7146_RPS_MEM … /* some i2c constants */ #define SAA7146_I2C_TIMEOUT … #define SAA7146_I2C_RETRIES … #define SAA7146_I2C_DELAY … /* unsorted defines */ #define ME1 … #define PV1 … /* gpio defines */ #define SAA7146_GPIO_INPUT … #define SAA7146_GPIO_IRQHI … #define SAA7146_GPIO_IRQLO … #define SAA7146_GPIO_IRQHL … #define SAA7146_GPIO_OUTLO … #define SAA7146_GPIO_OUTHI … /* debi defines */ #define DEBINOSWAP … /* define for the register programming sequencer (rps) */ #define CMD_NOP … #define CMD_CLR_EVENT … #define CMD_SET_EVENT … #define CMD_PAUSE … #define CMD_CHECK_LATE … #define CMD_UPLOAD … #define CMD_STOP … #define CMD_INTERRUPT … #define CMD_JUMP … #define CMD_WR_REG … #define CMD_RD_REG … #define CMD_WR_REG_MASK … #define CMD_OAN … #define CMD_INV … #define CMD_SIG4 … #define CMD_SIG3 … #define CMD_SIG2 … #define CMD_SIG1 … #define CMD_SIG0 … #define CMD_O_FID_B … #define CMD_E_FID_B … #define CMD_O_FID_A … #define CMD_E_FID_A … /* some events and command modifiers for rps1 squarewave generator */ #define EVT_HS … #define EVT_VBI_B … #define RPS_OAN … #define RPS_INV … #define GPIO3_MSK … /* Bit mask constants */ #define MASK_00 … #define MASK_01 … #define MASK_02 … #define MASK_03 … #define MASK_04 … #define MASK_05 … #define MASK_06 … #define MASK_07 … #define MASK_08 … #define MASK_09 … #define MASK_10 … #define MASK_11 … #define MASK_12 … #define MASK_13 … #define MASK_14 … #define MASK_15 … #define MASK_16 … #define MASK_17 … #define MASK_18 … #define MASK_19 … #define MASK_20 … #define MASK_21 … #define MASK_22 … #define MASK_23 … #define MASK_24 … #define MASK_25 … #define MASK_26 … #define MASK_27 … #define MASK_28 … #define MASK_29 … #define MASK_30 … #define MASK_31 … #define MASK_B0 … #define MASK_B1 … #define MASK_B2 … #define MASK_B3 … #define MASK_W0 … #define MASK_W1 … #define MASK_PA … #define MASK_PR … #define MASK_ER … #define MASK_NONE … /* register aliases */ #define BASE_ODD1 … #define BASE_EVEN1 … #define PROT_ADDR1 … #define PITCH1 … #define BASE_PAGE1 … #define NUM_LINE_BYTE1 … #define BASE_ODD2 … #define BASE_EVEN2 … #define PROT_ADDR2 … #define PITCH2 … #define BASE_PAGE2 … #define NUM_LINE_BYTE2 … #define BASE_ODD3 … #define BASE_EVEN3 … #define PROT_ADDR3 … #define PITCH3 … #define BASE_PAGE3 … #define NUM_LINE_BYTE3 … #define PCI_BT_V1 … #define PCI_BT_V2 … #define PCI_BT_V3 … #define PCI_BT_DEBI … #define PCI_BT_A … #define DD1_INIT … #define DD1_STREAM_B … #define DD1_STREAM_A … #define BRS_CTRL … #define HPS_CTRL … #define HPS_V_SCALE … #define HPS_V_GAIN … #define HPS_H_PRESCALE … #define HPS_H_SCALE … #define BCS_CTRL … #define CHROMA_KEY_RANGE … #define CLIP_FORMAT_CTRL … #define DEBI_CONFIG … #define DEBI_COMMAND … #define DEBI_PAGE … #define DEBI_AD … #define I2C_TRANSFER … #define I2C_STATUS … #define BASE_A1_IN … #define PROT_A1_IN … #define PAGE_A1_IN … #define BASE_A1_OUT … #define PROT_A1_OUT … #define PAGE_A1_OUT … #define BASE_A2_IN … #define PROT_A2_IN … #define PAGE_A2_IN … #define BASE_A2_OUT … #define PROT_A2_OUT … #define PAGE_A2_OUT … #define RPS_PAGE0 … #define RPS_PAGE1 … #define RPS_THRESH0 … #define RPS_THRESH1 … #define RPS_TOV0 … #define RPS_TOV1 … #define IER … #define GPIO_CTRL … #define EC1SSR … #define EC2SSR … #define ECT1R … #define ECT2R … #define ACON1 … #define ACON2 … #define MC1 … #define MC2 … #define RPS_ADDR0 … #define RPS_ADDR1 … #define ISR … #define PSR … #define SSR … #define EC1R … #define EC2R … #define PCI_VDP1 … #define PCI_VDP2 … #define PCI_VDP3 … #define PCI_ADP1 … #define PCI_ADP2 … #define PCI_ADP3 … #define PCI_ADP4 … #define PCI_DMA_DDP … #define LEVEL_REP … #define A_TIME_SLOT1 … #define A_TIME_SLOT2 … /* isr masks */ #define SPCI_PPEF … #define SPCI_PABO … #define SPCI_PPED … #define SPCI_RPS_I1 … #define SPCI_RPS_I0 … #define SPCI_RPS_LATE1 … #define SPCI_RPS_LATE0 … #define SPCI_RPS_E1 … #define SPCI_RPS_E0 … #define SPCI_RPS_TO1 … #define SPCI_RPS_TO0 … #define SPCI_UPLD … #define SPCI_DEBI_S … #define SPCI_DEBI_E … #define SPCI_IIC_S … #define SPCI_IIC_E … #define SPCI_A2_IN … #define SPCI_A2_OUT … #define SPCI_A1_IN … #define SPCI_A1_OUT … #define SPCI_AFOU … #define SPCI_V_PE … #define SPCI_VFOU … #define SPCI_FIDA … #define SPCI_FIDB … #define SPCI_PIN3 … #define SPCI_PIN2 … #define SPCI_PIN1 … #define SPCI_PIN0 … #define SPCI_ECS … #define SPCI_EC3S … #define SPCI_EC0S … /* i2c */ #define SAA7146_I2C_ABORT … #define SAA7146_I2C_SPERR … #define SAA7146_I2C_APERR … #define SAA7146_I2C_DTERR … #define SAA7146_I2C_DRERR … #define SAA7146_I2C_AL … #define SAA7146_I2C_ERR … #define SAA7146_I2C_BUSY … #define SAA7146_I2C_START … #define SAA7146_I2C_CONT … #define SAA7146_I2C_STOP … #define SAA7146_I2C_NOP … #define SAA7146_I2C_BUS_BIT_RATE_6400 … #define SAA7146_I2C_BUS_BIT_RATE_3200 … #define SAA7146_I2C_BUS_BIT_RATE_480 … #define SAA7146_I2C_BUS_BIT_RATE_320 … #define SAA7146_I2C_BUS_BIT_RATE_240 … #define SAA7146_I2C_BUS_BIT_RATE_120 … #define SAA7146_I2C_BUS_BIT_RATE_80 … #define SAA7146_I2C_BUS_BIT_RATE_60 … static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y) { … } static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y) { … } #endif
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