linux/drivers/media/platform/amphion/vpu_imx8q.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2020-2021 NXP
 */

#ifndef _AMPHION_VPU_IMX8Q_H
#define _AMPHION_VPU_IMX8Q_H

#define SCB_XREG_SLV_BASE …
#define SCB_SCB_BLK_CTRL …
#define SCB_BLK_CTRL_XMEM_RESET_SET …
#define SCB_BLK_CTRL_CACHE_RESET_SET …
#define SCB_BLK_CTRL_CACHE_RESET_CLR …
#define SCB_BLK_CTRL_SCB_CLK_ENABLE_SET …

#define XMEM_CONTROL …

#define MC_CACHE_0_BASE …
#define MC_CACHE_1_BASE …

#define DEC_MFD_XREG_SLV_BASE …
#define ENC_MFD_XREG_SLV_0_BASE …
#define ENC_MFD_XREG_SLV_1_BASE …

#define MFD_HIF …
#define MFD_HIF_MSD_REG_INTERRUPT_STATUS …
#define MFD_SIF …
#define MFD_SIF_CTRL_STATUS …
#define MFD_SIF_INTR_STATUS …
#define MFD_MCX …
#define MFD_MCX_OFF …
#define MFD_PIX_IF …

#define MFD_BLK_CTRL …
#define MFD_BLK_CTRL_MFD_SYS_RESET_SET …
#define MFD_BLK_CTRL_MFD_SYS_RESET_CLR …
#define MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET …
#define MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_CLR …

#define VID_API_NUM_STREAMS …
#define VID_API_MAX_BUF_PER_STR …
#define VID_API_MAX_NUM_MVC_VIEWS …
#define MEDIAIP_MAX_NUM_MALONES …
#define MEDIAIP_MAX_NUM_MALONE_IRQ_PINS …
#define MEDIAIP_MAX_NUM_WINDSORS …
#define MEDIAIP_MAX_NUM_WINDSOR_IRQ_PINS …
#define MEDIAIP_MAX_NUM_CMD_IRQ_PINS …
#define MEDIAIP_MAX_NUM_MSG_IRQ_PINS …
#define MEDIAIP_MAX_NUM_TIMER_IRQ_PINS …
#define MEDIAIP_MAX_NUM_TIMER_IRQ_SLOTS …

#define WINDSOR_PAL_IRQ_PIN_L …
#define WINDSOR_PAL_IRQ_PIN_H …

struct vpu_rpc_system_config { … };

int vpu_imx8q_setup_dec(struct vpu_dev *vpu);
int vpu_imx8q_setup_enc(struct vpu_dev *vpu);
int vpu_imx8q_setup(struct vpu_dev *vpu);
int vpu_imx8q_reset(struct vpu_dev *vpu);
int vpu_imx8q_set_system_cfg_common(struct vpu_rpc_system_config *config, u32 regs, u32 core_id);
int vpu_imx8q_boot_core(struct vpu_core *core);
int vpu_imx8q_get_power_state(struct vpu_core *core);
int vpu_imx8q_on_firmware_loaded(struct vpu_core *core);
int vpu_imx8q_check_memory_region(dma_addr_t base, dma_addr_t addr, u32 size);
bool vpu_imx8q_check_codec(enum vpu_core_type type);
bool vpu_imx8q_check_fmt(enum vpu_core_type type, u32 pixelfmt);

#endif