/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ /* * Wave5 series multi-standard codec IP - product config definitions * * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef _VPU_CONFIG_H_ #define _VPU_CONFIG_H_ #define WAVE515_CODE … #define WAVE517_CODE … #define WAVE537_CODE … #define WAVE511_CODE … #define WAVE521_CODE … #define WAVE521C_CODE … #define WAVE521C_DUAL_CODE … #define WAVE521E1_CODE … #define PRODUCT_CODE_W_SERIES(x) … #define WAVE517_WORKBUF_SIZE … #define WAVE521ENC_WORKBUF_SIZE … #define WAVE521DEC_WORKBUF_SIZE … #define WAVE515DEC_WORKBUF_SIZE … #define MAX_NUM_INSTANCE … #define W5_MIN_ENC_PIC_WIDTH … #define W5_MIN_ENC_PIC_HEIGHT … #define W5_MAX_ENC_PIC_WIDTH … #define W5_MAX_ENC_PIC_HEIGHT … // application specific configuration #define VPU_ENC_TIMEOUT … #define VPU_DEC_TIMEOUT … // for WAVE encoder #define USE_SRC_PRP_AXI … #define USE_SRC_PRI_AXI … #define DEFAULT_SRC_AXI … /************************************************************************/ /* VPU COMMON MEMORY */ /************************************************************************/ #define VLC_BUF_NUM … #define WAVE521_COMMAND_QUEUE_DEPTH … #define WAVE515_COMMAND_QUEUE_DEPTH … #define W5_REMAP_INDEX0 … #define W5_REMAP_INDEX1 … #define W5_REMAP_MAX_SIZE … #define WAVE521_MAX_CODE_BUF_SIZE … #define WAVE515_MAX_CODE_BUF_SIZE … #define WAVE5_TEMPBUF_SIZE … #define WAVE521_SIZE_COMMON … #define WAVE515_ONE_TASKBUF_SIZE … #define WAVE515_SIZE_COMMON … //=====4. VPU REPORT MEMORY ======================// #define WAVE5_UPPER_PROC_AXI_ID … #define WAVE5_PROC_AXI_ID … #define WAVE5_PRP_AXI_ID … #define WAVE5_FBD_Y_AXI_ID … #define WAVE5_FBC_Y_AXI_ID … #define WAVE5_FBD_C_AXI_ID … #define WAVE5_FBC_C_AXI_ID … #define WAVE5_SEC_AXI_ID … #define WAVE5_PRI_AXI_ID … #endif /* _VPU_CONFIG_H_ */
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