/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ /* * Wave5 series multi-standard codec IP - helper definitions * * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef VPUAPI_H_INCLUDED #define VPUAPI_H_INCLUDED #include <linux/idr.h> #include <linux/genalloc.h> #include <media/v4l2-device.h> #include <media/v4l2-mem2mem.h> #include <media/v4l2-ctrls.h> #include "wave5-vpuerror.h" #include "wave5-vpuconfig.h" #include "wave5-vdi.h" enum product_id { … }; struct vpu_attr; enum vpu_instance_type { … }; enum vpu_instance_state { … }; /* Maximum available on hardware. */ #define WAVE5_MAX_FBS … #define MAX_REG_FRAME … #define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) … #define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) … #define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) … #define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) … #define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) … #define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) … /* * common struct and definition */ enum cod_std { … }; enum wave_std { … }; enum set_param_option { … }; /************************************************************************/ /* PROFILE & LEVEL */ /************************************************************************/ /* HEVC */ #define HEVC_PROFILE_MAIN … #define HEVC_PROFILE_MAIN10 … #define HEVC_PROFILE_STILLPICTURE … #define HEVC_PROFILE_MAIN10_STILLPICTURE … /* H.264 profile for encoder*/ #define H264_PROFILE_BP … #define H264_PROFILE_MP … #define H264_PROFILE_EXTENDED … #define H264_PROFILE_HP … #define H264_PROFILE_HIGH10 … #define H264_PROFILE_HIGH422 … #define H264_PROFILE_HIGH444 … /************************************************************************/ /* error codes */ /************************************************************************/ /************************************************************************/ /* utility macros */ /************************************************************************/ /* Initialize sequence firmware command mode */ #define INIT_SEQ_NORMAL … /* Decode firmware command mode */ #define DEC_PIC_NORMAL … /* bit_alloc_mode */ #define BIT_ALLOC_MODE_FIXED_RATIO … /* bit_rate */ #define MAX_BIT_RATE … /* decoding_refresh_type */ #define DEC_REFRESH_TYPE_NON_IRAP … #define DEC_REFRESH_TYPE_CRA … #define DEC_REFRESH_TYPE_IDR … /* depend_slice_mode */ #define DEPEND_SLICE_MODE_RECOMMENDED … #define DEPEND_SLICE_MODE_BOOST … #define DEPEND_SLICE_MODE_FAST … /* hvs_max_delta_qp */ #define MAX_HVS_MAX_DELTA_QP … /* intra_refresh_mode */ #define REFRESH_MODE_CTU_ROWS … #define REFRESH_MODE_CTU_COLUMNS … #define REFRESH_MODE_CTU_STEP_SIZE … #define REFRESH_MODE_CTUS … /* intra_mb_refresh_mode */ #define REFRESH_MB_MODE_NONE … #define REFRESH_MB_MODE_CTU_ROWS … #define REFRESH_MB_MODE_CTU_COLUMNS … #define REFRESH_MB_MODE_CTU_STEP_SIZE … /* intra_qp */ #define MAX_INTRA_QP … /* nr_inter_weight_* */ #define MAX_INTER_WEIGHT … /* nr_intra_weight_* */ #define MAX_INTRA_WEIGHT … /* nr_noise_sigma_* */ #define MAX_NOISE_SIGMA … /* bitstream_buffer_size */ #define MIN_BITSTREAM_BUFFER_SIZE … #define MIN_BITSTREAM_BUFFER_SIZE_WAVE521 … /* vbv_buffer_size */ #define MIN_VBV_BUFFER_SIZE … #define MAX_VBV_BUFFER_SIZE … #define BUFFER_MARGIN … #define MAX_FIRMWARE_CALL_RETRY … #define VDI_LITTLE_ENDIAN … /* * Parameters of DEC_SET_SEQ_CHANGE_MASK */ #define SEQ_CHANGE_ENABLE_PROFILE … #define SEQ_CHANGE_ENABLE_SIZE … #define SEQ_CHANGE_ENABLE_BITDEPTH … #define SEQ_CHANGE_ENABLE_DPB_COUNT … #define SEQ_CHANGE_ENABLE_ASPECT_RATIO … #define SEQ_CHANGE_ENABLE_VIDEO_SIGNAL … #define SEQ_CHANGE_ENABLE_VUI_TIMING_INFO … #define SEQ_CHANGE_ENABLE_ALL_HEVC … #define SEQ_CHANGE_ENABLE_ALL_AVC … #define DISPLAY_IDX_FLAG_SEQ_END … #define DISPLAY_IDX_FLAG_NO_FB … #define DECODED_IDX_FLAG_NO_FB … #define DECODED_IDX_FLAG_SKIP … #define RECON_IDX_FLAG_ENC_END … #define RECON_IDX_FLAG_ENC_DELAY … #define RECON_IDX_FLAG_HEADER_ONLY … #define RECON_IDX_FLAG_CHANGE_PARAM … enum codec_command { … }; enum mirror_direction { … }; enum frame_buffer_format { … }; enum packed_format_num { … }; enum wave5_interrupt_bit { … }; enum pic_type { … }; enum sw_reset_mode { … }; enum tiled_map_type { … }; enum temporal_id_mode { … }; struct vpu_attr { … }; struct frame_buffer { … }; struct vpu_rect { … }; /* * decode struct and definition */ struct dec_open_param { … }; struct dec_initial_info { … }; struct dec_output_info { … }; struct queue_status_info { … }; /* * encode struct and definition */ #define MAX_NUM_TEMPORAL_LAYER … #define MAX_NUM_SPATIAL_LAYER … #define MAX_GOP_NUM … struct custom_gop_pic_param { … }; struct enc_wave_param { … }; struct enc_open_param { … }; struct enc_initial_info { … }; /* * Flags to encode NAL units explicitly */ struct enc_code_opt { … }; struct enc_param { … }; struct enc_output_info { … }; enum enc_pic_code_option { … }; enum gop_preset_idx { … }; struct sec_axi_info { … }; struct dec_info { … }; struct enc_info { … }; struct vpu_device { … }; struct vpu_instance; struct vpu_instance_ops { … }; struct vpu_instance { … }; void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data); u32 wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr); int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count, size_t size); int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset, u8 *data, size_t len); int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev); void wave5_vdi_free_sram(struct vpu_device *vpu_dev); int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size); int wave5_vpu_flush_instance(struct vpu_instance *inst); int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id); int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param); int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res); int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst); int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info); int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs, int num_of_display_fbs, int stride, int height); int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail); int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info); int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr); dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst); int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index); int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter); int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr, dma_addr_t *pwr_ptr, size_t *size); int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size); int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index); int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index); int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param); int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res); int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst); int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info); int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num, unsigned int stride, int height, enum tiled_map_type map_type); int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param, u32 *fail_res); int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info); int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter); #endif
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