/* SPDX-License-Identifier: GPL-2.0 */ /* * Marvell camera core structures. * * Copyright 2011 Jonathan Corbet [email protected] */ #ifndef _MCAM_CORE_H #define _MCAM_CORE_H #include <linux/list.h> #include <linux/clk-provider.h> #include <linux/workqueue.h> #include <media/v4l2-common.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-dev.h> #include <media/videobuf2-v4l2.h> /* * Create our own symbols for the supported buffer modes, but, for now, * base them entirely on which videobuf2 options have been selected. */ #if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC) #define MCAM_MODE_VMALLOC … #endif #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG) #define MCAM_MODE_DMA_CONTIG … #endif #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG) #define MCAM_MODE_DMA_SG … #endif #if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \ !defined(MCAM_MODE_DMA_SG) #error One of the vb2 buffer modes must be selected in the config #endif enum mcam_state { … }; #define MAX_DMA_BUFS … /* * Different platforms work best with different buffer modes, so we * let the platform pick. */ enum mcam_buffer_mode { … }; enum mcam_chip_id { … }; /* * Is a given buffer mode supported by the current kernel configuration? */ static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode) { … } /* * Basic frame states */ struct mcam_frame_state { … }; #define NR_MCAM_CLK … /* * A description of one of our devices. * Locking: controlled by s_mutex. Certain fields, however, require * the dev_lock spinlock; they are marked as such by comments. * dev_lock is also required for access to device registers. */ struct mcam_camera { … }; /* * Register I/O functions. These are here because the platform code * may legitimately need to mess with the register space. */ /* * Device register I/O */ static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg, unsigned int val) { … } static inline unsigned int mcam_reg_read(struct mcam_camera *cam, unsigned int reg) { … } static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg, unsigned int val, unsigned int mask) { … } static inline void mcam_reg_clear_bit(struct mcam_camera *cam, unsigned int reg, unsigned int val) { … } static inline void mcam_reg_set_bit(struct mcam_camera *cam, unsigned int reg, unsigned int val) { … } /* * Functions for use by platform code. */ int mccic_register(struct mcam_camera *cam); int mccic_irq(struct mcam_camera *cam, unsigned int irqs); void mccic_shutdown(struct mcam_camera *cam); void mccic_suspend(struct mcam_camera *cam); int mccic_resume(struct mcam_camera *cam); /* * Register definitions for the m88alp01 camera interface. Offsets in bytes * as given in the spec. */ #define REG_Y0BAR … #define REG_Y1BAR … #define REG_Y2BAR … #define REG_U0BAR … #define REG_U1BAR … #define REG_U2BAR … #define REG_V0BAR … #define REG_V1BAR … #define REG_V2BAR … /* * register definitions for MIPI support */ #define REG_CSI2_CTRL0 … #define CSI2_C0_MIPI_EN … #define CSI2_C0_ACT_LANE(n) … #define REG_CSI2_DPHY3 … #define REG_CSI2_DPHY5 … #define REG_CSI2_DPHY6 … /* ... */ #define REG_IMGPITCH … #define IMGP_YP_SHFT … #define IMGP_YP_MASK … #define IMGP_UVP_SHFT … #define IMGP_UVP_MASK … #define REG_IRQSTATRAW … #define IRQ_EOF0 … #define IRQ_EOF1 … #define IRQ_EOF2 … #define IRQ_SOF0 … #define IRQ_SOF1 … #define IRQ_SOF2 … #define IRQ_OVERFLOW … #define IRQ_TWSIW … #define IRQ_TWSIR … #define IRQ_TWSIE … #define TWSIIRQS … #define FRAMEIRQS … #define ALLIRQS … #define REG_IRQMASK … #define REG_IRQSTAT … #define REG_IMGSIZE … #define IMGSZ_V_MASK … #define IMGSZ_V_SHIFT … #define IMGSZ_H_MASK … #define REG_IMGOFFSET … #define REG_CTRL0 … #define C0_ENABLE … /* Mask for all the format bits */ #define C0_DF_MASK … /* RGB ordering */ #define C0_RGB4_RGBX … #define C0_RGB4_XRGB … #define C0_RGB4_BGRX … #define C0_RGB4_XBGR … #define C0_RGB5_RGGB … #define C0_RGB5_GRBG … #define C0_RGB5_GBRG … #define C0_RGB5_BGGR … /* Spec has two fields for DIN and DOUT, but they must match, so combine them here. */ #define C0_DF_YUV … #define C0_DF_RGB … #define C0_DF_BAYER … /* 8-8-8 must be missing from the below - ask */ #define C0_RGBF_565 … #define C0_RGBF_444 … #define C0_RGB_BGR … #define C0_YUV_PLANAR … #define C0_YUV_PACKED … #define C0_YUV_420PL … /* Think that 420 packed must be 111 - ask */ #define C0_YUVE_YUYV … #define C0_YUVE_YVYU … #define C0_YUVE_VYUY … #define C0_YUVE_UYVY … #define C0_YUVE_NOSWAP … #define C0_YUVE_SWAP13 … #define C0_YUVE_SWAP24 … #define C0_YUVE_SWAP1324 … /* Bayer bits 18,19 if needed */ #define C0_EOF_VSYNC … #define C0_VEDGE_CTRL … #define C0_HPOL_LOW … #define C0_VPOL_LOW … #define C0_VCLK_LOW … #define C0_DOWNSCALE … /* SIFMODE */ #define C0_SIF_HVSYNC … #define C0_SOF_NOSYNC … #define C0_SIFM_MASK … /* Bits below C1_444ALPHA are not present in Cafe */ #define REG_CTRL1 … #define C1_CLKGATE … #define C1_DESC_ENA … #define C1_DESC_3WORD … #define C1_444ALPHA … #define C1_ALPHA_SHFT … #define C1_DMAB32 … #define C1_DMAB16 … #define C1_DMAB64 … #define C1_DMAB_MASK … #define C1_TWOBUFS … #define C1_PWRDWN … #define REG_CLKCTRL … #define CLK_DIV_MASK … /* This appears to be a Cafe-only register */ #define REG_UBAR … /* Armada 610 DMA descriptor registers */ #define REG_DMA_DESC_Y … #define REG_DMA_DESC_U … #define REG_DMA_DESC_V … #define REG_DESC_LEN_Y … #define REG_DESC_LEN_U … #define REG_DESC_LEN_V … /* * Useful stuff that probably belongs somewhere global. */ #define VGA_WIDTH … #define VGA_HEIGHT … #endif /* _MCAM_CORE_H */
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