linux/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c

// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * Wave5 series multi-standard codec IP - helper functions
 *
 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
 */

#include <linux/bug.h>
#include "wave5-vpuapi.h"
#include "wave5-regdefine.h"
#include "wave5.h"

#define DECODE_ALL_TEMPORAL_LAYERS …
#define DECODE_ALL_SPATIAL_LAYERS …

static int wave5_initialize_vpu(struct device *dev, u8 *code, size_t size)
{ … }

int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size)
{ … }

int wave5_vpu_flush_instance(struct vpu_instance *inst)
{ … }

int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id)
{ … }

static int wave5_check_dec_open_param(struct vpu_instance *inst, struct dec_open_param *param)
{ … }

int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param)
{ … }

static int reset_auxiliary_buffers(struct vpu_instance *inst, unsigned int index)
{ … }

int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res)
{ … }

int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst)
{ … }

int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info)
{ … }

int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs,
					   int num_of_display_fbs, int stride, int height)
{ … }

int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr,
				       dma_addr_t *pwr_ptr, size_t *size)
{ … }

int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size)
{ … }

int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail)
{ … }

int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr)
{ … }

dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst)
{ … }

int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info)
{ … }

int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index)
{ … }

int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index)
{ … }

int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index)
{ … }

int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter)
{ … }

int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param)
{ … }

int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res)
{ … }

int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num,
					unsigned int stride, int height,
					enum tiled_map_type map_type)
{ … }

static int wave5_check_enc_param(struct vpu_instance *inst, struct enc_param *param)
{ … }

int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param, u32 *fail_res)
{ … }

int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info)
{ … }

int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter)
{ … }

int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst)
{ … }

int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info)
{ … }