// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) /* * Wave5 series multi-standard codec IP - wave5 backend logic * * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include <linux/iopoll.h> #include <linux/bitfield.h> #include "wave5-vpu.h" #include "wave5.h" #include "wave5-regdefine.h" #define FIO_TIMEOUT … #define FIO_CTRL_READY … #define FIO_CTRL_WRITE … #define VPU_BUSY_CHECK_TIMEOUT … #define QUEUE_REPORT_MASK … /* Encoder support fields */ #define W521_FEATURE_HEVC10BIT_ENC … #define W521_FEATURE_AVC10BIT_ENC … #define W521_FEATURE_AVC_ENCODER … #define W521_FEATURE_HEVC_ENCODER … /* Decoder support fields */ #define W521_FEATURE_AVC_DECODER … #define W521_FEATURE_HEVC_DECODER … #define W515_FEATURE_HEVC10BIT_DEC … #define W515_FEATURE_HEVC_DECODER … #define W521_FEATURE_BACKBONE … #define W521_FEATURE_VCORE_BACKBONE … #define W521_FEATURE_VCPU_BACKBONE … #define REMAP_CTRL_MAX_SIZE_BITS … #define REMAP_CTRL_REGISTER_VALUE(index) … #define FASTIO_ADDRESS_MASK … #define SEQ_PARAM_PROFILE_MASK … static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason, const char *func); #define PRINT_REG_ERR(dev, reason) … static inline const char *cmd_to_str(int cmd, bool is_dec) { … } static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason, const char *func) { … } static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val) { … } static void wave5_fio_writel(struct vpu_device *vpu_dev, unsigned int addr, unsigned int data) { … } static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) { … } static int wave5_wait_vpu_busy(struct vpu_device *vpu_dev, unsigned int addr) { … } static int wave5_wait_vcpu_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) { … } bool wave5_vpu_is_init(struct vpu_device *vpu_dev) { … } unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev) { … } static void wave5_bit_issue_command(struct vpu_device *vpu_dev, struct vpu_instance *inst, u32 cmd) { … } static int wave5_vpu_firmware_command_queue_error_check(struct vpu_device *dev, u32 *fail_res) { … } static int send_firmware_command(struct vpu_instance *inst, u32 cmd, bool check_success, u32 *queue_status, u32 *fail_result) { … } static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *inst, enum query_opt query_opt) { … } static void setup_wave5_interrupts(struct vpu_device *vpu_dev) { … } static int setup_wave5_properties(struct device *dev) { … } int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision) { … } static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index) { … } int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) { … } int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param) { … } int wave5_vpu_hw_flush_instance(struct vpu_instance *inst) { … } static u32 get_bitstream_options(struct dec_info *info) { … } int wave5_vpu_dec_init_seq(struct vpu_instance *inst) { … } static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initial_info *info) { … } int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info) { … } int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_buffer *fb_arr, enum tiled_map_type map_type, unsigned int count) { … } static u32 wave5_vpu_dec_validate_sec_axi(struct vpu_instance *inst) { … } int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res) { … } int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result) { … } int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) { … } static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, size_t size) { … } int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) { … } int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res) { … } int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos) { … } int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index) { … } int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index) { … } int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags) { … } dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst) { … } int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr) { … } /************************************************************************/ /* ENCODER functions */ /************************************************************************/ int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst, struct enc_open_param *open_param) { … } static void wave5_set_enc_crop_info(u32 codec, struct enc_wave_param *param, int rot_mode, int src_width, int src_height) { … } int wave5_vpu_enc_init_seq(struct vpu_instance *inst) { … } int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info) { … } static u32 calculate_luma_stride(u32 width, u32 bit_depth) { … } static u32 calculate_chroma_stride(u32 width, u32 bit_depth) { … } int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst, struct frame_buffer *fb_arr, enum tiled_map_type map_type, unsigned int count) { … } static u32 wave5_vpu_enc_validate_sec_axi(struct vpu_instance *inst) { … } int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res) { … } int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result) { … } int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res) { … } static bool wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst, struct enc_open_param *open_param) { … } static bool wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev, struct enc_open_param *open_param) { … } int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param) { … }
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