/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2021 MediaTek Inc. * Author: Yunfei Dong <[email protected]> */ #ifndef _MTK_VCODEC_DEC_HW_H_ #define _MTK_VCODEC_DEC_HW_H_ #include <linux/io.h> #include <linux/platform_device.h> #include "mtk_vcodec_dec_drv.h" #define VDEC_HW_ACTIVE_ADDR … #define VDEC_HW_ACTIVE_MASK … #define VDEC_IRQ_CFG … #define VDEC_IRQ_CLR … #define VDEC_IRQ_CFG_REG … #define IS_SUPPORT_VDEC_HW_IRQ(hw_idx) … /** * enum mtk_vdec_hw_reg_idx - subdev hardware register base index * @VDEC_HW_SYS : vdec soc register index * @VDEC_HW_MISC: vdec misc register index * @VDEC_HW_MAX : vdec supported max register index */ enum mtk_vdec_hw_reg_idx { … }; /** * struct mtk_vdec_hw_dev - vdec hardware driver data * @plat_dev: platform device * @main_dev: main device * @reg_base: mapped address of MTK Vcodec registers. * * @curr_ctx: the context that is waiting for codec hardware * * @dec_irq : decoder irq resource * @pm : power management control * @hw_idx : each hardware index */ struct mtk_vdec_hw_dev { … }; #endif /* _MTK_VCODEC_DEC_HW_H_ */