linux/drivers/media/platform/mediatek/mdp3/mdp_reg_wdma.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022 MediaTek Inc.
 * Author: Ping-Hsun Wu <[email protected]>
 */

#ifndef __MDP_REG_WDMA_H__
#define __MDP_REG_WDMA_H__

#define WDMA_EN
#define WDMA_RST
#define WDMA_CFG
#define WDMA_SRC_SIZE
#define WDMA_CLIP_SIZE
#define WDMA_CLIP_COORD
#define WDMA_DST_W_IN_BYTE
#define WDMA_ALPHA
#define WDMA_BUF_CON2
#define WDMA_DST_UV_PITCH
#define WDMA_DST_ADDR_OFFSET
#define WDMA_DST_U_ADDR_OFFSET
#define WDMA_DST_V_ADDR_OFFSET
#define WDMA_FLOW_CTRL_DBG
#define WDMA_DST_ADDR
#define WDMA_DST_U_ADDR
#define WDMA_DST_V_ADDR

/* MASK */
#define WDMA_EN_MASK
#define WDMA_RST_MASK
#define WDMA_CFG_MASK
#define WDMA_SRC_SIZE_MASK
#define WDMA_CLIP_SIZE_MASK
#define WDMA_CLIP_COORD_MASK
#define WDMA_DST_W_IN_BYTE_MASK
#define WDMA_ALPHA_MASK
#define WDMA_BUF_CON2_MASK
#define WDMA_DST_UV_PITCH_MASK
#define WDMA_DST_ADDR_OFFSET_MASK
#define WDMA_DST_U_ADDR_OFFSET_MASK
#define WDMA_DST_V_ADDR_OFFSET_MASK
#define WDMA_FLOW_CTRL_DBG_MASK
#define WDMA_DST_ADDR_MASK
#define WDMA_DST_U_ADDR_MASK
#define WDMA_DST_V_ADDR_MASK

#endif  // __MDP_REG_WDMA_H__