/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2019-2020 NXP */ #ifndef __IMX8_ISI_REGS_H__ #define __IMX8_ISI_REGS_H__ #include <linux/bits.h> /* ISI Registers Define */ /* Channel Control Register */ #define CHNL_CTRL … #define CHNL_CTRL_CHNL_EN … #define CHNL_CTRL_CLK_EN … #define CHNL_CTRL_CHNL_BYPASS … #define CHNL_CTRL_CHAIN_BUF(n) … #define CHNL_CTRL_CHAIN_BUF_MASK … #define CHNL_CTRL_CHAIN_BUF_NO_CHAIN … #define CHNL_CTRL_CHAIN_BUF_2_CHAIN … #define CHNL_CTRL_SW_RST … #define CHNL_CTRL_BLANK_PXL(n) … #define CHNL_CTRL_BLANK_PXL_MASK … #define CHNL_CTRL_MIPI_VC_ID(n) … #define CHNL_CTRL_MIPI_VC_ID_MASK … #define CHNL_CTRL_SRC_TYPE(n) … #define CHNL_CTRL_SRC_TYPE_MASK … #define CHNL_CTRL_SRC_TYPE_DEVICE … #define CHNL_CTRL_SRC_TYPE_MEMORY … #define CHNL_CTRL_SRC_INPUT(n) … #define CHNL_CTRL_SRC_INPUT_MASK … /* Channel Image Control Register */ #define CHNL_IMG_CTRL … #define CHNL_IMG_CTRL_FORMAT(n) … #define CHNL_IMG_CTRL_FORMAT_MASK … #define CHNL_IMG_CTRL_FORMAT_RGBA8888 … #define CHNL_IMG_CTRL_FORMAT_ABGR8888 … #define CHNL_IMG_CTRL_FORMAT_ARGB8888 … #define CHNL_IMG_CTRL_FORMAT_RGBX888 … #define CHNL_IMG_CTRL_FORMAT_XBGR888 … #define CHNL_IMG_CTRL_FORMAT_XRGB888 … #define CHNL_IMG_CTRL_FORMAT_RGB888P … #define CHNL_IMG_CTRL_FORMAT_BGR888P … #define CHNL_IMG_CTRL_FORMAT_A2BGR10 … #define CHNL_IMG_CTRL_FORMAT_A2RGB10 … #define CHNL_IMG_CTRL_FORMAT_RGB565 … #define CHNL_IMG_CTRL_FORMAT_RAW8 … #define CHNL_IMG_CTRL_FORMAT_RAW10 … #define CHNL_IMG_CTRL_FORMAT_RAW10P … #define CHNL_IMG_CTRL_FORMAT_RAW12 … #define CHNL_IMG_CTRL_FORMAT_RAW16 … #define CHNL_IMG_CTRL_FORMAT_YUV444_1P8P … #define CHNL_IMG_CTRL_FORMAT_YUV444_2P8P … #define CHNL_IMG_CTRL_FORMAT_YUV444_3P8P … #define CHNL_IMG_CTRL_FORMAT_YUV444_1P8 … #define CHNL_IMG_CTRL_FORMAT_YUV444_1P10 … #define CHNL_IMG_CTRL_FORMAT_YUV444_2P10 … #define CHNL_IMG_CTRL_FORMAT_YUV444_3P10 … #define CHNL_IMG_CTRL_FORMAT_YUV444_1P10P … #define CHNL_IMG_CTRL_FORMAT_YUV444_2P10P … #define CHNL_IMG_CTRL_FORMAT_YUV444_3P10P … #define CHNL_IMG_CTRL_FORMAT_YUV444_1P12 … #define CHNL_IMG_CTRL_FORMAT_YUV444_2P12 … #define CHNL_IMG_CTRL_FORMAT_YUV444_3P12 … #define CHNL_IMG_CTRL_FORMAT_YUV422_1P8P … #define CHNL_IMG_CTRL_FORMAT_YUV422_2P8P … #define CHNL_IMG_CTRL_FORMAT_YUV422_3P8P … #define CHNL_IMG_CTRL_FORMAT_YUV422_1P10 … #define CHNL_IMG_CTRL_FORMAT_YUV422_2P10 … #define CHNL_IMG_CTRL_FORMAT_YUV422_3P10 … #define CHNL_IMG_CTRL_FORMAT_YUV422_1P10P … #define CHNL_IMG_CTRL_FORMAT_YUV422_2P10P … #define CHNL_IMG_CTRL_FORMAT_YUV422_3P10P … #define CHNL_IMG_CTRL_FORMAT_YUV422_1P12 … #define CHNL_IMG_CTRL_FORMAT_YUV422_2P12 … #define CHNL_IMG_CTRL_FORMAT_YUV422_3P12 … #define CHNL_IMG_CTRL_FORMAT_YUV420_2P8P … #define CHNL_IMG_CTRL_FORMAT_YUV420_3P8P … #define CHNL_IMG_CTRL_FORMAT_YUV420_2P10 … #define CHNL_IMG_CTRL_FORMAT_YUV420_3P10 … #define CHNL_IMG_CTRL_FORMAT_YUV420_2P10P … #define CHNL_IMG_CTRL_FORMAT_YUV420_3P10P … #define CHNL_IMG_CTRL_FORMAT_YUV420_2P12 … #define CHNL_IMG_CTRL_FORMAT_YUV420_3P12 … #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) … #define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK … #define CHNL_IMG_CTRL_GBL_ALPHA_EN … #define CHNL_IMG_CTRL_DEINT(n) … #define CHNL_IMG_CTRL_DEINT_MASK … #define CHNL_IMG_CTRL_DEINT_WEAVE_ODD_EVEN … #define CHNL_IMG_CTRL_DEINT_WEAVE_EVEN_ODD … #define CHNL_IMG_CTRL_DEINT_BLEND_ODD_EVEN … #define CHNL_IMG_CTRL_DEINT_BLEND_EVEN_ODD … #define CHNL_IMG_CTRL_DEINT_LDOUBLE_ODD_EVEN … #define CHNL_IMG_CTRL_DEINT_LDOUBLE_EVEN_ODD … #define CHNL_IMG_CTRL_DEC_X(n) … #define CHNL_IMG_CTRL_DEC_X_MASK … #define CHNL_IMG_CTRL_DEC_Y(n) … #define CHNL_IMG_CTRL_DEC_Y_MASK … #define CHNL_IMG_CTRL_CROP_EN … #define CHNL_IMG_CTRL_VFLIP_EN … #define CHNL_IMG_CTRL_HFLIP_EN … #define CHNL_IMG_CTRL_YCBCR_MODE … #define CHNL_IMG_CTRL_CSC_MODE(n) … #define CHNL_IMG_CTRL_CSC_MODE_MASK … #define CHNL_IMG_CTRL_CSC_MODE_YUV2RGB … #define CHNL_IMG_CTRL_CSC_MODE_YCBCR2RGB … #define CHNL_IMG_CTRL_CSC_MODE_RGB2YUV … #define CHNL_IMG_CTRL_CSC_MODE_RGB2YCBCR … #define CHNL_IMG_CTRL_CSC_BYPASS … /* Channel Output Buffer Control Register */ #define CHNL_OUT_BUF_CTRL … #define CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR … #define CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(n) … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_NO_PANIC … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_25 … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_50 … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_75 … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(n) … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_NO_PANIC … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_25 … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_50 … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_75 … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(n) … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_NO_PANIC … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_25 … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_50 … #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_75 … /* Channel Image Configuration */ #define CHNL_IMG_CFG … #define CHNL_IMG_CFG_HEIGHT(n) … #define CHNL_IMG_CFG_HEIGHT_MASK … #define CHNL_IMG_CFG_WIDTH(n) … #define CHNL_IMG_CFG_WIDTH_MASK … /* Channel Interrupt Enable Register */ #define CHNL_IER … #define CHNL_IER_MEM_RD_DONE_EN … #define CHNL_IER_LINE_RCVD_EN … #define CHNL_IER_FRM_RCVD_EN … #define CHNL_IER_AXI_WR_ERR_V_EN … #define CHNL_IER_AXI_WR_ERR_U_EN … #define CHNL_IER_AXI_WR_ERR_Y_EN … #define CHNL_IER_AXI_RD_ERR_EN … /* Channel Status Register */ #define CHNL_STS … #define CHNL_STS_MEM_RD_DONE … #define CHNL_STS_LINE_STRD … #define CHNL_STS_FRM_STRD … #define CHNL_STS_AXI_WR_ERR_V … #define CHNL_STS_AXI_WR_ERR_U … #define CHNL_STS_AXI_WR_ERR_Y … #define CHNL_STS_AXI_RD_ERR … #define CHNL_STS_OFLW_PANIC_V_BUF … #define CHNL_STS_EXCS_OFLW_V_BUF … #define CHNL_STS_OFLW_V_BUF … #define CHNL_STS_OFLW_PANIC_U_BUF … #define CHNL_STS_EXCS_OFLW_U_BUF … #define CHNL_STS_OFLW_U_BUF … #define CHNL_STS_OFLW_PANIC_Y_BUF … #define CHNL_STS_EXCS_OFLW_Y_BUF … #define CHNL_STS_OFLW_Y_BUF … #define CHNL_STS_EARLY_VSYNC_ERR … #define CHNL_STS_LATE_VSYNC_ERR … #define CHNL_STS_MEM_RD_OFLOW … #define CHNL_STS_BUF2_ACTIVE … #define CHNL_STS_BUF1_ACTIVE … #define CHNL_STS_OFLW_BYTES(n) … #define CHNL_STS_OFLW_BYTES_MASK … /* Channel Scale Factor Register */ #define CHNL_SCALE_FACTOR … #define CHNL_SCALE_FACTOR_Y_SCALE(n) … #define CHNL_SCALE_FACTOR_Y_SCALE_MASK … #define CHNL_SCALE_FACTOR_X_SCALE(n) … #define CHNL_SCALE_FACTOR_X_SCALE_MASK … /* Channel Scale Offset Register */ #define CHNL_SCALE_OFFSET … #define CHNL_SCALE_OFFSET_Y_SCALE(n) … #define CHNL_SCALE_OFFSET_Y_SCALE_MASK … #define CHNL_SCALE_OFFSET_X_SCALE(n) … #define CHNL_SCALE_OFFSET_X_SCALE_MASK … /* Channel Crop Upper Left Corner Coordinate Register */ #define CHNL_CROP_ULC … #define CHNL_CROP_ULC_X(n) … #define CHNL_CROP_ULC_X_MASK … #define CHNL_CROP_ULC_Y(n) … #define CHNL_CROP_ULC_Y_MASK … /* Channel Crop Lower Right Corner Coordinate Register */ #define CHNL_CROP_LRC … #define CHNL_CROP_LRC_X(n) … #define CHNL_CROP_LRC_X_MASK … #define CHNL_CROP_LRC_Y(n) … #define CHNL_CROP_LRC_Y_MASK … /* Channel Color Space Conversion Coefficient Register 0 */ #define CHNL_CSC_COEFF0 … #define CHNL_CSC_COEFF0_A2(n) … #define CHNL_CSC_COEFF0_A2_MASK … #define CHNL_CSC_COEFF0_A1(n) … #define CHNL_CSC_COEFF0_A1_MASK … /* Channel Color Space Conversion Coefficient Register 1 */ #define CHNL_CSC_COEFF1 … #define CHNL_CSC_COEFF1_B1(n) … #define CHNL_CSC_COEFF1_B1_MASK … #define CHNL_CSC_COEFF1_A3(n) … #define CHNL_CSC_COEFF1_A3_MASK … /* Channel Color Space Conversion Coefficient Register 2 */ #define CHNL_CSC_COEFF2 … #define CHNL_CSC_COEFF2_B3(n) … #define CHNL_CSC_COEFF2_B3_MASK … #define CHNL_CSC_COEFF2_B2(n) … #define CHNL_CSC_COEFF2_B2_MASK … /* Channel Color Space Conversion Coefficient Register 3 */ #define CHNL_CSC_COEFF3 … #define CHNL_CSC_COEFF3_C2(n) … #define CHNL_CSC_COEFF3_C2_MASK … #define CHNL_CSC_COEFF3_C1(n) … #define CHNL_CSC_COEFF3_C1_MASK … /* Channel Color Space Conversion Coefficient Register 4 */ #define CHNL_CSC_COEFF4 … #define CHNL_CSC_COEFF4_D1(n) … #define CHNL_CSC_COEFF4_D1_MASK … #define CHNL_CSC_COEFF4_C3(n) … #define CHNL_CSC_COEFF4_C3_MASK … /* Channel Color Space Conversion Coefficient Register 5 */ #define CHNL_CSC_COEFF5 … #define CHNL_CSC_COEFF5_D3(n) … #define CHNL_CSC_COEFF5_D3_MASK … #define CHNL_CSC_COEFF5_D2(n) … #define CHNL_CSC_COEFF5_D2_MASK … /* Channel Alpha Value Register for ROI 0 */ #define CHNL_ROI_0_ALPHA … #define CHNL_ROI_0_ALPHA_VAL(n) … #define CHNL_ROI_0_ALPHA_MASK … #define CHNL_ROI_0_ALPHA_EN … /* Channel Upper Left Coordinate Register for ROI 0 */ #define CHNL_ROI_0_ULC … #define CHNL_ROI_0_ULC_X(n) … #define CHNL_ROI_0_ULC_X_MASK … #define CHNL_ROI_0_ULC_Y(n) … #define CHNL_ROI_0_ULC_Y_MASK … /* Channel Lower Right Coordinate Register for ROI 0 */ #define CHNL_ROI_0_LRC … #define CHNL_ROI_0_LRC_X(n) … #define CHNL_ROI_0_LRC_X_MASK … #define CHNL_ROI_0_LRC_Y(n) … #define CHNL_ROI_0_LRC_Y_MASK … /* Channel Alpha Value Register for ROI 1 */ #define CHNL_ROI_1_ALPHA … #define CHNL_ROI_1_ALPHA_VAL(n) … #define CHNL_ROI_1_ALPHA_MASK … #define CHNL_ROI_1_ALPHA_EN … /* Channel Upper Left Coordinate Register for ROI 1 */ #define CHNL_ROI_1_ULC … #define CHNL_ROI_1_ULC_X(n) … #define CHNL_ROI_1_ULC_X_MASK … #define CHNL_ROI_1_ULC_Y(n) … #define CHNL_ROI_1_ULC_Y_MASK … /* Channel Lower Right Coordinate Register for ROI 1 */ #define CHNL_ROI_1_LRC … #define CHNL_ROI_1_LRC_X(n) … #define CHNL_ROI_1_LRC_X_MASK … #define CHNL_ROI_1_LRC_Y(n) … #define CHNL_ROI_1_LRC_Y_MASK … /* Channel Alpha Value Register for ROI 2 */ #define CHNL_ROI_2_ALPHA … #define CHNL_ROI_2_ALPHA_VAL(n) … #define CHNL_ROI_2_ALPHA_MASK … #define CHNL_ROI_2_ALPHA_EN … /* Channel Upper Left Coordinate Register for ROI 2 */ #define CHNL_ROI_2_ULC … #define CHNL_ROI_2_ULC_X(n) … #define CHNL_ROI_2_ULC_X_MASK … #define CHNL_ROI_2_ULC_Y(n) … #define CHNL_ROI_2_ULC_Y_MASK … /* Channel Lower Right Coordinate Register for ROI 2 */ #define CHNL_ROI_2_LRC … #define CHNL_ROI_2_LRC_X(n) … #define CHNL_ROI_2_LRC_X_MASK … #define CHNL_ROI_2_LRC_Y(n) … #define CHNL_ROI_2_LRC_Y_MASK … /* Channel Alpha Value Register for ROI 3 */ #define CHNL_ROI_3_ALPHA … #define CHNL_ROI_3_ALPHA_VAL(n) … #define CHNL_ROI_3_ALPHA_MASK … #define CHNL_ROI_3_ALPHA_EN … /* Channel Upper Left Coordinate Register for ROI 3 */ #define CHNL_ROI_3_ULC … #define CHNL_ROI_3_ULC_X(n) … #define CHNL_ROI_3_ULC_X_MASK … #define CHNL_ROI_3_ULC_Y(n) … #define CHNL_ROI_3_ULC_Y_MASK … /* Channel Lower Right Coordinate Register for ROI 3 */ #define CHNL_ROI_3_LRC … #define CHNL_ROI_3_LRC_X(n) … #define CHNL_ROI_3_LRC_X_MASK … #define CHNL_ROI_3_LRC_Y(n) … #define CHNL_ROI_3_LRC_Y_MASK … /* Channel RGB or Luma (Y) Output Buffer 1 Address */ #define CHNL_OUT_BUF1_ADDR_Y … /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */ #define CHNL_OUT_BUF1_ADDR_U … /* Channel Chroma (V/Cr) Output Buffer 1 Address */ #define CHNL_OUT_BUF1_ADDR_V … /* Channel Output Buffer Pitch */ #define CHNL_OUT_BUF_PITCH … #define CHNL_OUT_BUF_PITCH_LINE_PITCH(n) … #define CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK … /* Channel Input Buffer Address */ #define CHNL_IN_BUF_ADDR … /* Channel Input Buffer Pitch */ #define CHNL_IN_BUF_PITCH … #define CHNL_IN_BUF_PITCH_FRM_PITCH(n) … #define CHNL_IN_BUF_PITCH_FRM_PITCH_MASK … #define CHNL_IN_BUF_PITCH_LINE_PITCH(n) … #define CHNL_IN_BUF_PITCH_LINE_PITCH_MASK … /* Channel Memory Read Control */ #define CHNL_MEM_RD_CTRL … #define CHNL_MEM_RD_CTRL_IMG_TYPE(n) … #define CHNL_MEM_RD_CTRL_IMG_TYPE_MASK … #define CHNL_MEM_RD_CTRL_IMG_TYPE_BGR8P … #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB8P … #define CHNL_MEM_RD_CTRL_IMG_TYPE_XRGB8 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGBX8 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_XBGR8 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB565 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_A2BGR10 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_A2RGB10 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8P … #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10P … #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P12 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P8P … #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P10 … #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P12 … #define CHNL_MEM_RD_CTRL_READ_MEM … /* Channel RGB or Luma (Y) Output Buffer 2 Address */ #define CHNL_OUT_BUF2_ADDR_Y … /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */ #define CHNL_OUT_BUF2_ADDR_U … /* Channel Chroma (V/Cr) Output Buffer 2 Address */ #define CHNL_OUT_BUF2_ADDR_V … /* Channel scale image config */ #define CHNL_SCL_IMG_CFG … #define CHNL_SCL_IMG_CFG_HEIGHT(n) … #define CHNL_SCL_IMG_CFG_HEIGHT_MASK … #define CHNL_SCL_IMG_CFG_WIDTH(n) … #define CHNL_SCL_IMG_CFG_WIDTH_MASK … /* Channel Flow Control Register */ #define CHNL_FLOW_CTRL … #define CHNL_FLOW_CTRL_FC_DENOM_MASK … #define CHNL_FLOW_CTRL_FC_DENOM(n) … #define CHNL_FLOW_CTRL_FC_NUMER_MASK … #define CHNL_FLOW_CTRL_FC_NUMER(n) … /* Channel Output Y-Buffer 1 Extended Address Bits */ #define CHNL_Y_BUF1_XTND_ADDR … /* Channel Output U-Buffer 1 Extended Address Bits */ #define CHNL_U_BUF1_XTND_ADDR … /* Channel Output V-Buffer 1 Extended Address Bits */ #define CHNL_V_BUF1_XTND_ADDR … /* Channel Output Y-Buffer 2 Extended Address Bits */ #define CHNL_Y_BUF2_XTND_ADDR … /* Channel Output U-Buffer 2 Extended Address Bits */ #define CHNL_U_BUF2_XTND_ADDR … /* Channel Output V-Buffer 2 Extended Address Bits */ #define CHNL_V_BUF2_XTND_ADDR … /* Channel Input Buffer Extended Address Bits */ #define CHNL_IN_BUF_XTND_ADDR … #endif /* __IMX8_ISI_REGS_H__ */
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