linux/drivers/media/platform/qcom/camss/camss-csid-gen2.c

// SPDX-License-Identifier: GPL-2.0
/*
 * camss-csid-4-7.c
 *
 * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
 *
 * Copyright (C) 2020 Linaro Ltd.
 */
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>

#include "camss-csid.h"
#include "camss-csid-gen2.h"
#include "camss.h"

/* The CSID 2 IP-block is different from the others,
 * and is of a bare-bones Lite version, with no PIX
 * interface support. As a result of that it has an
 * alternate register layout.
 */

#define CSID_HW_VERSION
#define HW_VERSION_STEPPING
#define HW_VERSION_REVISION
#define HW_VERSION_GENERATION

#define CSID_RST_STROBES
#define RST_STROBES

#define CSID_CSI2_RX_IRQ_STATUS
#define CSID_CSI2_RX_IRQ_MASK
#define CSID_CSI2_RX_IRQ_CLEAR

#define CSID_CSI2_RDIN_IRQ_STATUS(rdi)
#define CSID_CSI2_RDIN_IRQ_MASK(rdi)
#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi)
#define CSID_CSI2_RDIN_IRQ_SET(rdi)

#define CSID_TOP_IRQ_STATUS
#define TOP_IRQ_STATUS_RESET_DONE
#define CSID_TOP_IRQ_MASK
#define CSID_TOP_IRQ_CLEAR
#define CSID_TOP_IRQ_SET
#define CSID_IRQ_CMD
#define IRQ_CMD_CLEAR
#define IRQ_CMD_SET

#define CSID_CSI2_RX_CFG0
#define CSI2_RX_CFG0_NUM_ACTIVE_LANES
#define CSI2_RX_CFG0_DL0_INPUT_SEL
#define CSI2_RX_CFG0_DL1_INPUT_SEL
#define CSI2_RX_CFG0_DL2_INPUT_SEL
#define CSI2_RX_CFG0_DL3_INPUT_SEL
#define CSI2_RX_CFG0_PHY_NUM_SEL
#define CSI2_RX_CFG0_PHY_TYPE_SEL

#define CSID_CSI2_RX_CFG1
#define CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN
#define CSI2_RX_CFG1_DE_SCRAMBLE_EN
#define CSI2_RX_CFG1_VC_MODE
#define CSI2_RX_CFG1_COMPLETE_STREAM_EN
#define CSI2_RX_CFG1_COMPLETE_STREAM_FRAME_TIMING
#define CSI2_RX_CFG1_MISR_EN
#define CSI2_RX_CFG1_CGC_MODE
#define CGC_MODE_DYNAMIC_GATING
#define CGC_MODE_ALWAYS_ON

#define CSID_RDI_CFG0(rdi)
#define RDI_CFG0_BYTE_CNTR_EN
#define RDI_CFG0_FORMAT_MEASURE_EN
#define RDI_CFG0_TIMESTAMP_EN
#define RDI_CFG0_DROP_H_EN
#define RDI_CFG0_DROP_V_EN
#define RDI_CFG0_CROP_H_EN
#define RDI_CFG0_CROP_V_EN
#define RDI_CFG0_MISR_EN
#define RDI_CFG0_CGC_MODE
#define CGC_MODE_DYNAMIC
#define CGC_MODE_ALWAYS_ON
#define RDI_CFG0_PLAIN_ALIGNMENT
#define PLAIN_ALIGNMENT_LSB
#define PLAIN_ALIGNMENT_MSB
#define RDI_CFG0_PLAIN_FORMAT
#define RDI_CFG0_DECODE_FORMAT
#define RDI_CFG0_DATA_TYPE
#define RDI_CFG0_VIRTUAL_CHANNEL
#define RDI_CFG0_DT_ID
#define RDI_CFG0_EARLY_EOF_EN
#define RDI_CFG0_PACKING_FORMAT
#define RDI_CFG0_ENABLE

#define CSID_RDI_CFG1(rdi)
#define RDI_CFG1_TIMESTAMP_STB_SEL

#define CSID_RDI_CTRL(rdi)
#define RDI_CTRL_HALT_CMD
#define HALT_CMD_HALT_AT_FRAME_BOUNDARY
#define HALT_CMD_RESUME_AT_FRAME_BOUNDARY
#define RDI_CTRL_HALT_MODE

#define CSID_RDI_FRM_DROP_PATTERN(rdi)
#define CSID_RDI_FRM_DROP_PERIOD(rdi)
#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi)
#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi)
#define CSID_RDI_RPP_PIX_DROP_PATTERN(rdi)
#define CSID_RDI_RPP_PIX_DROP_PERIOD(rdi)
#define CSID_RDI_RPP_LINE_DROP_PATTERN(rdi)
#define CSID_RDI_RPP_LINE_DROP_PERIOD(rdi)

#define CSID_TPG_CTRL
#define TPG_CTRL_TEST_EN
#define TPG_CTRL_FS_PKT_EN
#define TPG_CTRL_FE_PKT_EN
#define TPG_CTRL_NUM_ACTIVE_LANES
#define TPG_CTRL_CYCLES_BETWEEN_PKTS
#define TPG_CTRL_NUM_TRAIL_BYTES

#define CSID_TPG_VC_CFG0
#define TPG_VC_CFG0_VC_NUM
#define TPG_VC_CFG0_NUM_ACTIVE_SLOTS
#define NUM_ACTIVE_SLOTS_0_ENABLED
#define NUM_ACTIVE_SLOTS_0_1_ENABLED
#define NUM_ACTIVE_SLOTS_0_1_2_ENABLED
#define NUM_ACTIVE_SLOTS_0_1_3_ENABLED
#define TPG_VC_CFG0_LINE_INTERLEAVING_MODE
#define INTELEAVING_MODE_INTERLEAVED
#define INTELEAVING_MODE_ONE_SHOT
#define TPG_VC_CFG0_NUM_FRAMES

#define CSID_TPG_VC_CFG1
#define TPG_VC_CFG1_H_BLANKING_COUNT
#define TPG_VC_CFG1_V_BLANKING_COUNT
#define TPG_VC_CFG1_V_BLANK_FRAME_WIDTH_SEL

#define CSID_TPG_LFSR_SEED

#define CSID_TPG_DT_n_CFG_0(n)
#define TPG_DT_n_CFG_0_FRAME_HEIGHT
#define TPG_DT_n_CFG_0_FRAME_WIDTH

#define CSID_TPG_DT_n_CFG_1(n)
#define TPG_DT_n_CFG_1_DATA_TYPE
#define TPG_DT_n_CFG_1_ECC_XOR_MASK
#define TPG_DT_n_CFG_1_CRC_XOR_MASK

#define CSID_TPG_DT_n_CFG_2(n)
#define TPG_DT_n_CFG_2_PAYLOAD_MODE
#define TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD
#define TPG_DT_n_CFG_2_ENCODE_FORMAT

#define CSID_TPG_COLOR_BARS_CFG
#define TPG_COLOR_BARS_CFG_UNICOLOR_BAR_EN
#define TPG_COLOR_BARS_CFG_UNICOLOR_BAR_SEL
#define TPG_COLOR_BARS_CFG_SPLIT_EN
#define TPG_COLOR_BARS_CFG_ROTATE_PERIOD

#define CSID_TPG_COLOR_BOX_CFG
#define TPG_COLOR_BOX_CFG_MODE
#define TPG_COLOR_BOX_PATTERN_SEL

static void __csid_configure_rx(struct csid_device *csid,
				struct csid_phy_config *phy, int vc)
{}

static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
{}

static void __csid_configure_testgen(struct csid_device *csid, u8 enable, u8 vc)
{}

static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
{}

static void csid_configure_stream(struct csid_device *csid, u8 enable)
{}

static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
{}

/*
 * csid_hw_version - CSID hardware version query
 * @csid: CSID device
 *
 * Return HW version or error
 */
static u32 csid_hw_version(struct csid_device *csid)
{}

/*
 * csid_isr - CSID module interrupt service routine
 * @irq: Interrupt line
 * @dev: CSID device
 *
 * Return IRQ_HANDLED on success
 */
static irqreturn_t csid_isr(int irq, void *dev)
{}

/*
 * csid_reset - Trigger reset on CSID module and wait to complete
 * @csid: CSID device
 *
 * Return 0 on success or a negative error code otherwise
 */
static int csid_reset(struct csid_device *csid)
{}

static u32 csid_src_pad_code(struct csid_device *csid, u32 sink_code,
			     unsigned int match_format_idx, u32 match_code)
{}

static void csid_subdev_init(struct csid_device *csid)
{}

const struct csid_hw_ops csid_ops_gen2 =;