/* SPDX-License-Identifier: GPL-2.0-only */ /* * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver * * Copyright (C) 2013 Samsung Electronics Co., Ltd. * * Authors: Sylwester Nawrocki <[email protected]> * Younghwan Joo <[email protected]> */ #ifndef FIMC_IS_REG_H_ #define FIMC_IS_REG_H_ /* WDT_ISP register */ #define REG_WDT_ISP … /* MCUCTL registers base offset */ #define MCUCTL_BASE … /* MCU Controller Register */ #define MCUCTL_REG_MCUCTRL … #define MCUCTRL_MSWRST … /* Boot Base Offset Address Register */ #define MCUCTL_REG_BBOAR … /* Interrupt Generation Register 0 from Host CPU to VIC */ #define MCUCTL_REG_INTGR0 … /* __n = 0...9 */ #define INTGR0_INTGC(__n) … /* __n = 0...5 */ #define INTGR0_INTGD(__n) … /* Interrupt Clear Register 0 from Host CPU to VIC */ #define MCUCTL_REG_INTCR0 … /* __n = 0...9 */ #define INTCR0_INTGC(__n) … /* __n = 0...5 */ #define INTCR0_INTCD(__n) … /* Interrupt Mask Register 0 from Host CPU to VIC */ #define MCUCTL_REG_INTMR0 … /* __n = 0...9 */ #define INTMR0_INTMC(__n) … /* __n = 0...5 */ #define INTMR0_INTMD(__n) … /* Interrupt Status Register 0 from Host CPU to VIC */ #define MCUCTL_REG_INTSR0 … /* __n (bit number) = 0...4 */ #define INTSR0_GET_INTSD(x, __n) … /* __n (bit number) = 0...9 */ #define INTSR0_GET_INTSC(x, __n) … /* Interrupt Mask Status Register 0 from Host CPU to VIC */ #define MCUCTL_REG_INTMSR0 … /* __n (bit number) = 0...4 */ #define INTMSR0_GET_INTMSD(x, __n) … /* __n (bit number) = 0...9 */ #define INTMSR0_GET_INTMSC(x, __n) … /* Interrupt Generation Register 1 from ISP CPU to Host IC */ #define MCUCTL_REG_INTGR1 … /* __n = 0...9 */ #define INTGR1_INTGC(__n) … /* Interrupt Clear Register 1 from ISP CPU to Host IC */ #define MCUCTL_REG_INTCR1 … /* __n = 0...9 */ #define INTCR1_INTCC(__n) … /* Interrupt Mask Register 1 from ISP CPU to Host IC */ #define MCUCTL_REG_INTMR1 … /* __n = 0...9 */ #define INTMR1_INTMC(__n) … /* Interrupt Status Register 1 from ISP CPU to Host IC */ #define MCUCTL_REG_INTSR1 … /* Interrupt Mask Status Register 1 from ISP CPU to Host IC */ #define MCUCTL_REG_INTMSR1 … /* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */ #define MCUCTL_REG_INTCR2 … /* __n = 0...5 */ #define INTCR2_INTCC(__n) … /* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */ #define MCUCTL_REG_INTMR2 … /* __n = 0...25 */ #define INTMR2_INTMCIS(__n) … /* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */ #define MCUCTL_REG_INTSR2 … /* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */ #define MCUCTL_REG_INTMSR2 … /* General Purpose Output Control Register (0~17) */ #define MCUCTL_REG_GPOCTLR … /* __n = 0...17 */ #define GPOCTLR_GPOG(__n) … /* General Purpose Pad Output Enable Register (0~17) */ #define MCUCTL_REG_GPOENCTLR … /* __n = 0...17 */ #define GPOENCTLR_GPOEN(__n) … /* General Purpose Input Control Register (0~17) */ #define MCUCTL_REG_GPICTLR … /* Shared registers between ISP CPU and the host CPU - ISSRxx */ /* ISSR(1): Command Host -> IS */ /* ISSR(1): Sensor ID for Command, ISSR2...5 = Parameter 1...4 */ /* ISSR(10): Reply IS -> Host */ /* ISSR(11): Sensor ID for Reply, ISSR12...15 = Parameter 1...4 */ /* ISSR(20): ISP_FRAME_DONE : SENSOR ID */ /* ISSR(21): ISP_FRAME_DONE : PARAMETER 1 */ /* ISSR(24): SCALERC_FRAME_DONE : SENSOR ID */ /* ISSR(25): SCALERC_FRAME_DONE : PARAMETER 1 */ /* ISSR(28): 3DNR_FRAME_DONE : SENSOR ID */ /* ISSR(29): 3DNR_FRAME_DONE : PARAMETER 1 */ /* ISSR(32): SCALERP_FRAME_DONE : SENSOR ID */ /* ISSR(33): SCALERP_FRAME_DONE : PARAMETER 1 */ /* __n = 0...63 */ #define MCUCTL_REG_ISSR(__n) … /* PMU ISP register offsets */ #define REG_CMU_RESET_ISP_SYS_PWR_REG … #define REG_CMU_SYSCLK_ISP_SYS_PWR_REG … #define REG_PMU_ISP_ARM_SYS … #define REG_PMU_ISP_ARM_CONFIGURATION … #define REG_PMU_ISP_ARM_STATUS … #define REG_PMU_ISP_ARM_OPTION … void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int bit); void fimc_is_fw_clear_irq2(struct fimc_is *is); int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num); void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is); int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is); void fimc_is_hw_set_sensor_num(struct fimc_is *is); void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask); void fimc_is_hw_stream_on(struct fimc_is *is); void fimc_is_hw_stream_off(struct fimc_is *is); int fimc_is_hw_set_param(struct fimc_is *is); int fimc_is_hw_change_mode(struct fimc_is *is); void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index); void fimc_is_hw_get_setfile_addr(struct fimc_is *is); void fimc_is_hw_load_setfile(struct fimc_is *is); void fimc_is_hw_subip_power_off(struct fimc_is *is); int fimc_is_itf_s_param(struct fimc_is *is, bool update); int fimc_is_itf_mode_change(struct fimc_is *is); #endif /* FIMC_IS_REG_H_ */
Codebase Browser
linux