/* SPDX-License-Identifier: GPL-2.0-only */ /* * Register definition file for s3c24xx/s3c64xx SoC CAMIF driver * * Copyright (C) 2012 Sylwester Nawrocki <[email protected]> * Copyright (C) 2012 Tomasz Figa <[email protected]> */ #ifndef CAMIF_REGS_H_ #define CAMIF_REGS_H_ #include <linux/bitops.h> #include "camif-core.h" #include <media/drv-intf/s3c_camif.h> /* * The id argument indicates the processing path: * id = 0 - codec (FIMC C), 1 - preview (FIMC P). */ /* Camera input format */ #define S3C_CAMIF_REG_CISRCFMT … #define CISRCFMT_ITU601_8BIT … #define CISRCFMT_ITU656_8BIT … #define CISRCFMT_ORDER422_YCBYCR … #define CISRCFMT_ORDER422_YCRYCB … #define CISRCFMT_ORDER422_CBYCRY … #define CISRCFMT_ORDER422_CRYCBY … #define CISRCFMT_ORDER422_MASK … #define CISRCFMT_SIZE_CAM_MASK … /* Window offset */ #define S3C_CAMIF_REG_CIWDOFST … #define CIWDOFST_WINOFSEN … #define CIWDOFST_CLROVCOFIY … #define CIWDOFST_CLROVRLB_PR … /* #define CIWDOFST_CLROVPRFIY BIT(27) */ #define CIWDOFST_CLROVCOFICB … #define CIWDOFST_CLROVCOFICR … #define CIWDOFST_CLROVPRFICB … #define CIWDOFST_CLROVPRFICR … #define CIWDOFST_OFST_MASK … /* Window offset 2 */ #define S3C_CAMIF_REG_CIWDOFST2 … #define CIWDOFST2_OFST2_MASK … /* Global control */ #define S3C_CAMIF_REG_CIGCTRL … #define CIGCTRL_SWRST … #define CIGCTRL_CAMRST … #define CIGCTRL_TESTPATTERN_NORMAL … #define CIGCTRL_TESTPATTERN_COLOR_BAR … #define CIGCTRL_TESTPATTERN_HOR_INC … #define CIGCTRL_TESTPATTERN_VER_INC … #define CIGCTRL_TESTPATTERN_MASK … #define CIGCTRL_INVPOLPCLK … #define CIGCTRL_INVPOLVSYNC … #define CIGCTRL_INVPOLHREF … #define CIGCTRL_IRQ_OVFEN … #define CIGCTRL_HREF_MASK … #define CIGCTRL_IRQ_LEVEL … /* IRQ_CLR_C, IRQ_CLR_P */ #define CIGCTRL_IRQ_CLR(id) … #define CIGCTRL_FIELDMODE … #define CIGCTRL_INVPOLFIELD … #define CIGCTRL_CAM_INTERLACE … /* Y DMA output frame start address. n = 0..3. */ #define S3C_CAMIF_REG_CIYSA(id, n) … /* Cb plane output DMA start address. n = 0..3. Only codec path. */ #define S3C_CAMIF_REG_CICBSA(id, n) … /* Cr plane output DMA start address. n = 0..3. Only codec path. */ #define S3C_CAMIF_REG_CICRSA(id, n) … /* CICOTRGFMT, CIPRTRGFMT - Target format */ #define S3C_CAMIF_REG_CITRGFMT(id, _offs) … #define CITRGFMT_IN422 … #define CITRGFMT_OUT422 … #define CITRGFMT_OUTFORMAT_YCBCR420 … #define CITRGFMT_OUTFORMAT_YCBCR422 … #define CITRGFMT_OUTFORMAT_YCBCR422I … #define CITRGFMT_OUTFORMAT_RGB … #define CITRGFMT_OUTFORMAT_MASK … #define CITRGFMT_TARGETHSIZE(x) … #define CITRGFMT_FLIP_NORMAL … #define CITRGFMT_FLIP_X_MIRROR … #define CITRGFMT_FLIP_Y_MIRROR … #define CITRGFMT_FLIP_180 … #define CITRGFMT_FLIP_MASK … /* Preview path only */ #define CITRGFMT_ROT90_PR … #define CITRGFMT_TARGETVSIZE(x) … #define CITRGFMT_TARGETSIZE_MASK … /* CICOCTRL, CIPRCTRL. Output DMA control. */ #define S3C_CAMIF_REG_CICTRL(id, _offs) … #define CICTRL_BURST_MASK … /* xBURSTn - 5-bits width */ #define CICTRL_YBURST1(x) … #define CICTRL_YBURST2(x) … #define CICTRL_RGBBURST1(x) … #define CICTRL_RGBBURST2(x) … #define CICTRL_CBURST1(x) … #define CICTRL_CBURST2(x) … #define CICTRL_LASTIRQ_ENABLE … #define CICTRL_ORDER422_MASK … /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */ #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) … /* CICOSCPREDST, CIPRSCPREDST. Pre-scaler control 2. */ #define S3C_CAMIF_REG_CISCPREDST(id, _offs) … /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */ #define S3C_CAMIF_REG_CISCCTRL(id, _offs) … #define CISCCTRL_SCALERBYPASS … /* s3c244x preview path only, s3c64xx both */ #define CIPRSCCTRL_SAMPLE … /* 0 - 16-bit RGB, 1 - 24-bit RGB */ #define CIPRSCCTRL_RGB_FORMAT_24BIT … #define CIPRSCCTRL_SCALEUP_H … #define CIPRSCCTRL_SCALEUP_V … /* s3c64xx */ #define CISCCTRL_SCALEUP_H … #define CISCCTRL_SCALEUP_V … #define CISCCTRL_SCALEUP_MASK … #define CISCCTRL_CSCR2Y_WIDE … #define CISCCTRL_CSCY2R_WIDE … #define CISCCTRL_LCDPATHEN_FIFO … #define CISCCTRL_INTERLACE … #define CISCCTRL_SCALERSTART … #define CISCCTRL_INRGB_FMT_RGB565 … #define CISCCTRL_INRGB_FMT_RGB666 … #define CISCCTRL_INRGB_FMT_RGB888 … #define CISCCTRL_INRGB_FMT_MASK … #define CISCCTRL_OUTRGB_FMT_RGB565 … #define CISCCTRL_OUTRGB_FMT_RGB666 … #define CISCCTRL_OUTRGB_FMT_RGB888 … #define CISCCTRL_OUTRGB_FMT_MASK … #define CISCCTRL_EXTRGB_EXTENSION … #define CISCCTRL_ONE2ONE … #define CISCCTRL_MAIN_RATIO_MASK … /* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */ #define S3C_CAMIF_REG_CITAREA(id, _offs) … #define CITAREA_MASK … /* Codec (id = 0) or preview (id = 1) path status. */ #define S3C_CAMIF_REG_CISTATUS(id, _offs) … #define CISTATUS_OVFIY_STATUS … #define CISTATUS_OVFICB_STATUS … #define CISTATUS_OVFICR_STATUS … #define CISTATUS_OVF_MASK … #define CIPRSTATUS_OVF_MASK … #define CISTATUS_VSYNC_STATUS … #define CISTATUS_FRAMECNT_MASK … #define CISTATUS_FRAMECNT(__reg) … #define CISTATUS_WINOFSTEN_STATUS … #define CISTATUS_IMGCPTEN_STATUS … #define CISTATUS_IMGCPTENSC_STATUS … #define CISTATUS_VSYNC_A_STATUS … #define CISTATUS_FRAMEEND_STATUS … /* Image capture enable */ #define S3C_CAMIF_REG_CIIMGCPT(_offs) … #define CIIMGCPT_IMGCPTEN … #define CIIMGCPT_IMGCPTEN_SC(id) … /* Frame control: 1 - one-shot, 0 - free run */ #define CIIMGCPT_CPT_FREN_ENABLE(id) … #define CIIMGCPT_CPT_FRMOD_ENABLE … #define CIIMGCPT_CPT_FRMOD_CNT … /* Capture sequence */ #define S3C_CAMIF_REG_CICPTSEQ … /* Image effects */ #define S3C_CAMIF_REG_CIIMGEFF(_offs) … #define CIIMGEFF_IE_ENABLE(id) … #define CIIMGEFF_IE_ENABLE_MASK … /* Image effect: 1 - after scaler, 0 - before scaler */ #define CIIMGEFF_IE_AFTER_SC … #define CIIMGEFF_FIN_MASK … #define CIIMGEFF_FIN_BYPASS … #define CIIMGEFF_FIN_ARBITRARY … #define CIIMGEFF_FIN_NEGATIVE … #define CIIMGEFF_FIN_ARTFREEZE … #define CIIMGEFF_FIN_EMBOSSING … #define CIIMGEFF_FIN_SILHOUETTE … #define CIIMGEFF_PAT_CBCR_MASK … #define CIIMGEFF_PAT_CB(x) … #define CIIMGEFF_PAT_CR(x) … /* MSCOY0SA, MSPRY0SA. Y/Cb/Cr frame start address for input DMA. */ #define S3C_CAMIF_REG_MSY0SA(id) … #define S3C_CAMIF_REG_MSCB0SA(id) … #define S3C_CAMIF_REG_MSCR0SA(id) … /* MSCOY0END, MSCOY0END. Y/Cb/Cr frame end address for input DMA. */ #define S3C_CAMIF_REG_MSY0END(id) … #define S3C_CAMIF_REG_MSCB0END(id) … #define S3C_CAMIF_REG_MSCR0END(id) … /* MSPRYOFF, MSPRYOFF. Y/Cb/Cr offset. n: 0 - codec, 1 - preview. */ #define S3C_CAMIF_REG_MSYOFF(id) … #define S3C_CAMIF_REG_MSCBOFF(id) … #define S3C_CAMIF_REG_MSCROFF(id) … /* Real input DMA data size. n = 0 - codec, 1 - preview. */ #define S3C_CAMIF_REG_MSWIDTH(id) … #define AUTOLOAD_ENABLE … #define ADDR_CH_DIS … #define MSHEIGHT(x) … #define MSWIDTH(x) … /* Input DMA control. n = 0 - codec, 1 - preview */ #define S3C_CAMIF_REG_MSCTRL(id) … #define MSCTRL_ORDER422_M_YCBYCR … #define MSCTRL_ORDER422_M_YCRYCB … #define MSCTRL_ORDER422_M_CBYCRY … #define MSCTRL_ORDER422_M_CRYCBY … /* 0 - camera, 1 - DMA */ #define MSCTRL_SEL_DMA_CAM … #define MSCTRL_INFORMAT_M_YCBCR420 … #define MSCTRL_INFORMAT_M_YCBCR422 … #define MSCTRL_INFORMAT_M_YCBCR422I … #define MSCTRL_INFORMAT_M_RGB … #define MSCTRL_ENVID_M … /* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */ #define S3C_CAMIF_REG_CISSY(id) … #define S3C_CAMIF_REG_CISSCB(id) … #define S3C_CAMIF_REG_CISSCR(id) … #define S3C_CISS_OFFS_INITIAL(x) … #define S3C_CISS_OFFS_LINE(x) … /* ------------------------------------------------------------------ */ void camif_hw_reset(struct camif_dev *camif); void camif_hw_clear_pending_irq(struct camif_vp *vp); void camif_hw_clear_fifo_overflow(struct camif_vp *vp); void camif_hw_set_lastirq(struct camif_vp *vp, int enable); void camif_hw_set_input_path(struct camif_vp *vp); void camif_hw_enable_scaler(struct camif_vp *vp, bool on); void camif_hw_enable_capture(struct camif_vp *vp); void camif_hw_disable_capture(struct camif_vp *vp); void camif_hw_set_camera_bus(struct camif_dev *camif); void camif_hw_set_source_format(struct camif_dev *camif); void camif_hw_set_camera_crop(struct camif_dev *camif); void camif_hw_set_scaler(struct camif_vp *vp); void camif_hw_set_flip(struct camif_vp *vp); void camif_hw_set_output_dma(struct camif_vp *vp); void camif_hw_set_target_format(struct camif_vp *vp); void camif_hw_set_test_pattern(struct camif_dev *camif, unsigned int pattern); void camif_hw_set_effect(struct camif_dev *camif, unsigned int effect, unsigned int cr, unsigned int cb); void camif_hw_set_output_addr(struct camif_vp *vp, struct camif_addr *paddr, int index); void camif_hw_dump_regs(struct camif_dev *camif, const char *label); static inline u32 camif_hw_get_status(struct camif_vp *vp) { … } #endif /* CAMIF_REGS_H_ */
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