/* SPDX-License-Identifier: GPL-2.0-only */ /* linux/drivers/media/platform/samsung/s5p-jpeg/jpeg-regs.h * * Register definition file for Samsung JPEG codec driver * * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Author: Andrzej Pietrasiewicz <[email protected]> * Author: Jacek Anaszewski <[email protected]> */ #ifndef JPEG_REGS_H_ #define JPEG_REGS_H_ /* Register and bit definitions for S5PC210 */ /* JPEG mode register */ #define S5P_JPGMOD … #define S5P_PROC_MODE_MASK … #define S5P_PROC_MODE_DECOMPR … #define S5P_PROC_MODE_COMPR … #define S5P_SUBSAMPLING_MODE_MASK … #define S5P_SUBSAMPLING_MODE_444 … #define S5P_SUBSAMPLING_MODE_422 … #define S5P_SUBSAMPLING_MODE_420 … #define S5P_SUBSAMPLING_MODE_GRAY … /* JPEG operation status register */ #define S5P_JPGOPR … /* Quantization tables*/ #define S5P_JPG_QTBL … #define S5P_QT_NUMt_SHIFT(t) … #define S5P_QT_NUMt_MASK(t) … /* Huffman tables */ #define S5P_JPG_HTBL … #define S5P_HT_NUMt_AC_SHIFT(t) … #define S5P_HT_NUMt_AC_MASK(t) … #define S5P_HT_NUMt_DC_SHIFT(t) … #define S5P_HT_NUMt_DC_MASK(t) … /* JPEG restart interval register upper byte */ #define S5P_JPGDRI_U … /* JPEG restart interval register lower byte */ #define S5P_JPGDRI_L … /* JPEG vertical resolution register upper byte */ #define S5P_JPGY_U … /* JPEG vertical resolution register lower byte */ #define S5P_JPGY_L … /* JPEG horizontal resolution register upper byte */ #define S5P_JPGX_U … /* JPEG horizontal resolution register lower byte */ #define S5P_JPGX_L … /* JPEG byte count register upper byte */ #define S5P_JPGCNT_U … /* JPEG byte count register middle byte */ #define S5P_JPGCNT_M … /* JPEG byte count register lower byte */ #define S5P_JPGCNT_L … /* JPEG interrupt setting register */ #define S5P_JPGINTSE … #define S5P_RSTm_INT_EN_MASK … #define S5P_RSTm_INT_EN … #define S5P_DATA_NUM_INT_EN_MASK … #define S5P_DATA_NUM_INT_EN … #define S5P_FINAL_MCU_NUM_INT_EN_MASK … #define S5P_FINAL_MCU_NUM_INT_EN … /* JPEG interrupt status register */ #define S5P_JPGINTST … #define S5P_RESULT_STAT_SHIFT … #define S5P_RESULT_STAT_MASK … #define S5P_STREAM_STAT_SHIFT … #define S5P_STREAM_STAT_MASK … /* JPEG command register */ #define S5P_JPGCOM … #define S5P_INT_RELEASE … /* Raw image data r/w address register */ #define S5P_JPG_IMGADR … /* JPEG file r/w address register */ #define S5P_JPG_JPGADR … /* Coefficient for RGB-to-YCbCr converter register */ #define S5P_JPG_COEF(n) … #define S5P_COEFn_SHIFT(j) … #define S5P_COEFn_MASK(j) … /* JPEG color mode register */ #define S5P_JPGCMOD … #define S5P_MOD_SEL_MASK … #define S5P_MOD_SEL_422 … #define S5P_MOD_SEL_565 … #define S5P_MODE_Y16_MASK … #define S5P_MODE_Y16 … /* JPEG clock control register */ #define S5P_JPGCLKCON … #define S5P_CLK_DOWN_READY … #define S5P_POWER_ON … /* JPEG start register */ #define S5P_JSTART … /* JPEG SW reset register */ #define S5P_JPG_SW_RESET … /* JPEG timer setting register */ #define S5P_JPG_TIMER_SE … #define S5P_TIMER_INT_EN_MASK … #define S5P_TIMER_INT_EN … #define S5P_TIMER_INIT_MASK … /* JPEG timer status register */ #define S5P_JPG_TIMER_ST … #define S5P_TIMER_INT_STAT_SHIFT … #define S5P_TIMER_INT_STAT_MASK … #define S5P_TIMER_CNT_SHIFT … #define S5P_TIMER_CNT_MASK … /* JPEG decompression output format register */ #define S5P_JPG_OUTFORM … #define S5P_DEC_OUT_FORMAT_MASK … #define S5P_DEC_OUT_FORMAT_422 … #define S5P_DEC_OUT_FORMAT_420 … /* JPEG version register */ #define S5P_JPG_VERSION … /* JPEG compressed stream size interrupt setting register */ #define S5P_JPG_ENC_STREAM_INTSE … #define S5P_ENC_STREAM_INT_MASK … #define S5P_ENC_STREAM_INT_EN … #define S5P_ENC_STREAM_BOUND_MASK … /* JPEG compressed stream size interrupt status register */ #define S5P_JPG_ENC_STREAM_INTST … #define S5P_ENC_STREAM_INT_STAT_MASK … /* JPEG quantizer table register */ #define S5P_JPG_QTBL_CONTENT(n) … /* JPEG DC Huffman table register */ #define S5P_JPG_HDCTBL(n) … /* JPEG DC Huffman table register */ #define S5P_JPG_HDCTBLG(n) … /* JPEG AC Huffman table register */ #define S5P_JPG_HACTBL(n) … /* JPEG AC Huffman table register */ #define S5P_JPG_HACTBLG(n) … /* Register and bit definitions for Exynos 4x12 */ /* JPEG Codec Control Registers */ #define EXYNOS4_JPEG_CNTL_REG … #define EXYNOS4_INT_EN_REG … #define EXYNOS4_INT_TIMER_COUNT_REG … #define EXYNOS4_INT_STATUS_REG … #define EXYNOS4_OUT_MEM_BASE_REG … #define EXYNOS4_JPEG_IMG_SIZE_REG … #define EXYNOS4_IMG_BA_PLANE_1_REG … #define EXYNOS4_IMG_SO_PLANE_1_REG … #define EXYNOS4_IMG_PO_PLANE_1_REG … #define EXYNOS4_IMG_BA_PLANE_2_REG … #define EXYNOS4_IMG_SO_PLANE_2_REG … #define EXYNOS4_IMG_PO_PLANE_2_REG … #define EXYNOS4_IMG_BA_PLANE_3_REG … #define EXYNOS4_IMG_SO_PLANE_3_REG … #define EXYNOS4_IMG_PO_PLANE_3_REG … #define EXYNOS4_TBL_SEL_REG … #define EXYNOS4_IMG_FMT_REG … #define EXYNOS4_BITSTREAM_SIZE_REG … #define EXYNOS4_PADDING_REG … #define EXYNOS4_HUFF_CNT_REG … #define EXYNOS4_FIFO_STATUS_REG … #define EXYNOS4_DECODE_XY_SIZE_REG … #define EXYNOS4_DECODE_IMG_FMT_REG … #define EXYNOS4_QUAN_TBL_ENTRY_REG … #define EXYNOS4_HUFF_TBL_ENTRY_REG … /****************************************************************/ /* Bit definition part */ /****************************************************************/ /* JPEG CNTL Register bit */ #define EXYNOS4_ENC_DEC_MODE_MASK … #define EXYNOS4_DEC_MODE … #define EXYNOS4_ENC_MODE … #define EXYNOS4_AUTO_RST_MARKER … #define EXYNOS4_RST_INTERVAL_SHIFT … #define EXYNOS4_RST_INTERVAL(x) … #define EXYNOS4_HUF_TBL_EN … #define EXYNOS4_HOR_SCALING_SHIFT … #define EXYNOS4_HOR_SCALING_MASK … #define EXYNOS4_HOR_SCALING(x) … #define EXYNOS4_VER_SCALING_SHIFT … #define EXYNOS4_VER_SCALING_MASK … #define EXYNOS4_VER_SCALING(x) … #define EXYNOS4_PADDING … #define EXYNOS4_SYS_INT_EN … #define EXYNOS4_SOFT_RESET_HI … /* JPEG INT Register bit */ #define EXYNOS4_INT_EN_MASK … #define EXYNOS5433_INT_EN_MASK … #define EXYNOS4_PROT_ERR_INT_EN … #define EXYNOS4_IMG_COMPLETION_INT_EN … #define EXYNOS4_DEC_INVALID_FORMAT_EN … #define EXYNOS4_MULTI_SCAN_ERROR_EN … #define EXYNOS4_FRAME_ERR_EN … #define EXYNOS4_INT_EN_ALL … #define EXYNOS5433_INT_EN_ALL … #define EXYNOS4_MOD_REG_PROC_ENC … #define EXYNOS4_MOD_REG_PROC_DEC … #define EXYNOS4_MOD_REG_SUBSAMPLE_444 … #define EXYNOS4_MOD_REG_SUBSAMPLE_422 … #define EXYNOS4_MOD_REG_SUBSAMPLE_420 … #define EXYNOS4_MOD_REG_SUBSAMPLE_GRAY … /* JPEG IMAGE SIZE Register bit */ #define EXYNOS4_X_SIZE_SHIFT … #define EXYNOS4_X_SIZE_MASK … #define EXYNOS4_X_SIZE(x) … #define EXYNOS4_Y_SIZE_SHIFT … #define EXYNOS4_Y_SIZE_MASK … #define EXYNOS4_Y_SIZE(x) … /* JPEG IMAGE FORMAT Register bit */ #define EXYNOS4_ENC_IN_FMT_MASK … #define EXYNOS4_ENC_GRAY_IMG … #define EXYNOS4_ENC_RGB_IMG … #define EXYNOS4_ENC_YUV_444_IMG … #define EXYNOS4_ENC_YUV_422_IMG … #define EXYNOS4_ENC_YUV_440_IMG … #define EXYNOS4_DEC_GRAY_IMG … #define EXYNOS4_DEC_RGB_IMG … #define EXYNOS4_DEC_YUV_444_IMG … #define EXYNOS4_DEC_YUV_422_IMG … #define EXYNOS4_DEC_YUV_420_IMG … #define EXYNOS4_GRAY_IMG_IP_SHIFT … #define EXYNOS4_GRAY_IMG_IP_MASK … #define EXYNOS4_GRAY_IMG_IP … #define EXYNOS4_RGB_IP_SHIFT … #define EXYNOS4_RGB_IP_MASK … #define EXYNOS4_RGB_IP_RGB_16BIT_IMG … #define EXYNOS4_RGB_IP_RGB_32BIT_IMG … #define EXYNOS4_YUV_444_IP_SHIFT … #define EXYNOS4_YUV_444_IP_MASK … #define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG … #define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG … #define EXYNOS4_YUV_422_IP_SHIFT … #define EXYNOS4_YUV_422_IP_MASK … #define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG … #define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG … #define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG … #define EXYNOS4_YUV_420_IP_SHIFT … #define EXYNOS4_YUV_420_IP_MASK … #define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG … #define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG … #define EXYNOS4_ENC_FMT_SHIFT … #define EXYNOS4_ENC_FMT_MASK … #define EXYNOS5433_ENC_FMT_MASK … #define EXYNOS4_ENC_FMT_GRAY … #define EXYNOS4_ENC_FMT_YUV_444 … #define EXYNOS4_ENC_FMT_YUV_422 … #define EXYNOS4_ENC_FMT_YUV_420 … #define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK … #define EXYNOS4_SWAP_CHROMA_CRCB … #define EXYNOS4_SWAP_CHROMA_CBCR … #define EXYNOS5433_SWAP_CHROMA_CRCB … #define EXYNOS5433_SWAP_CHROMA_CBCR … /* JPEG HUFF count Register bit */ #define EXYNOS4_HUFF_COUNT_MASK … /* JPEG Decoded_img_x_y_size Register bit */ #define EXYNOS4_DECODED_SIZE_MASK … /* JPEG Decoded image format Register bit */ #define EXYNOS4_DECODED_IMG_FMT_MASK … /* JPEG TBL SEL Register bit */ #define EXYNOS4_Q_TBL_COMP(c, n) … #define EXYNOS4_Q_TBL_COMP1_0 … #define EXYNOS4_Q_TBL_COMP1_1 … #define EXYNOS4_Q_TBL_COMP1_2 … #define EXYNOS4_Q_TBL_COMP1_3 … #define EXYNOS4_Q_TBL_COMP2_0 … #define EXYNOS4_Q_TBL_COMP2_1 … #define EXYNOS4_Q_TBL_COMP2_2 … #define EXYNOS4_Q_TBL_COMP2_3 … #define EXYNOS4_Q_TBL_COMP3_0 … #define EXYNOS4_Q_TBL_COMP3_1 … #define EXYNOS4_Q_TBL_COMP3_2 … #define EXYNOS4_Q_TBL_COMP3_3 … #define EXYNOS4_HUFF_TBL_COMP(c, n) … #define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_0 … #define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_1 … #define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_0 … #define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_1 … #define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_0 … #define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_1 … #define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_0 … #define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_1 … #define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_0 … #define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_1 … #define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_0 … #define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_1 … #define EXYNOS4_NF_SHIFT … #define EXYNOS4_NF_MASK … #define EXYNOS4_NF(x) … /* JPEG quantizer table register */ #define EXYNOS4_QTBL_CONTENT(n) … /* JPEG DC luminance (code length) Huffman table register */ #define EXYNOS4_HUFF_TBL_HDCLL … /* JPEG DC luminance (values) Huffman table register */ #define EXYNOS4_HUFF_TBL_HDCLV … /* JPEG DC chrominance (code length) Huffman table register */ #define EXYNOS4_HUFF_TBL_HDCCL … /* JPEG DC chrominance (values) Huffman table register */ #define EXYNOS4_HUFF_TBL_HDCCV … /* JPEG AC luminance (code length) Huffman table register */ #define EXYNOS4_HUFF_TBL_HACLL … /* JPEG AC luminance (values) Huffman table register */ #define EXYNOS4_HUFF_TBL_HACLV … /* JPEG AC chrominance (code length) Huffman table register */ #define EXYNOS4_HUFF_TBL_HACCL … /* JPEG AC chrominance (values) Huffman table register */ #define EXYNOS4_HUFF_TBL_HACCV … /* Register and bit definitions for Exynos 3250 */ /* JPEG mode register */ #define EXYNOS3250_JPGMOD … #define EXYNOS3250_PROC_MODE_MASK … #define EXYNOS3250_PROC_MODE_DECOMPR … #define EXYNOS3250_PROC_MODE_COMPR … #define EXYNOS3250_SUBSAMPLING_MODE_MASK … #define EXYNOS3250_SUBSAMPLING_MODE_444 … #define EXYNOS3250_SUBSAMPLING_MODE_422 … #define EXYNOS3250_SUBSAMPLING_MODE_420 … #define EXYNOS3250_SUBSAMPLING_MODE_411 … #define EXYNOS3250_SUBSAMPLING_MODE_GRAY … /* JPEG operation status register */ #define EXYNOS3250_JPGOPR … #define EXYNOS3250_JPGOPR_MASK … /* Quantization and Huffman tables register */ #define EXYNOS3250_QHTBL … #define EXYNOS3250_QT_NUM_SHIFT(t) … #define EXYNOS3250_QT_NUM_MASK(t) … /* Huffman tables */ #define EXYNOS3250_HT_NUM_AC_SHIFT(t) … #define EXYNOS3250_HT_NUM_AC_MASK(t) … #define EXYNOS3250_HT_NUM_DC_SHIFT(t) … #define EXYNOS3250_HT_NUM_DC_MASK(t) … /* JPEG restart interval register */ #define EXYNOS3250_JPGDRI … #define EXYNOS3250_JPGDRI_MASK … /* JPEG vertical resolution register */ #define EXYNOS3250_JPGY … #define EXYNOS3250_JPGY_MASK … /* JPEG horizontal resolution register */ #define EXYNOS3250_JPGX … #define EXYNOS3250_JPGX_MASK … /* JPEG byte count register */ #define EXYNOS3250_JPGCNT … #define EXYNOS3250_JPGCNT_MASK … /* JPEG interrupt mask register */ #define EXYNOS3250_JPGINTSE … #define EXYNOS3250_JPEG_DONE_EN … #define EXYNOS3250_WDMA_DONE_EN … #define EXYNOS3250_RDMA_DONE_EN … #define EXYNOS3250_ENC_STREAM_INT_EN … #define EXYNOS3250_CORE_DONE_EN … #define EXYNOS3250_ERR_INT_EN … #define EXYNOS3250_HEAD_INT_EN … /* JPEG interrupt status register */ #define EXYNOS3250_JPGINTST … #define EXYNOS3250_JPEG_DONE … #define EXYNOS3250_WDMA_DONE … #define EXYNOS3250_RDMA_DONE … #define EXYNOS3250_ENC_STREAM_STAT … #define EXYNOS3250_RESULT_STAT … #define EXYNOS3250_STREAM_STAT … #define EXYNOS3250_HEADER_STAT … /* * Base address of the luma component DMA buffer * of the raw input or output image. */ #define EXYNOS3250_LUMA_BASE … #define EXYNOS3250_SRC_TILE_EN_MASK … /* Stride of source or destination luma raw image buffer */ #define EXYNOS3250_LUMA_STRIDE … /* Horizontal/vertical offset of active region in luma raw image buffer */ #define EXYNOS3250_LUMA_XY_OFFSET … #define EXYNOS3250_LUMA_YY_OFFSET_SHIFT … #define EXYNOS3250_LUMA_YY_OFFSET_MASK … #define EXYNOS3250_LUMA_YX_OFFSET_SHIFT … #define EXYNOS3250_LUMA_YX_OFFSET_MASK … /* * Base address of the chroma(Cb) component DMA buffer * of the raw input or output image. */ #define EXYNOS3250_CHROMA_BASE … /* Stride of source or destination chroma(Cb) raw image buffer */ #define EXYNOS3250_CHROMA_STRIDE … /* Horizontal/vertical offset of active region in chroma(Cb) raw image buffer */ #define EXYNOS3250_CHROMA_XY_OFFSET … #define EXYNOS3250_CHROMA_YY_OFFSET_SHIFT … #define EXYNOS3250_CHROMA_YY_OFFSET_MASK … #define EXYNOS3250_CHROMA_YX_OFFSET_SHIFT … #define EXYNOS3250_CHROMA_YX_OFFSET_MASK … /* * Base address of the chroma(Cr) component DMA buffer * of the raw input or output image. */ #define EXYNOS3250_CHROMA_CR_BASE … /* Stride of source or destination chroma(Cr) raw image buffer */ #define EXYNOS3250_CHROMA_CR_STRIDE … /* Horizontal/vertical offset of active region in chroma(Cb) raw image buffer */ #define EXYNOS3250_CHROMA_CR_XY_OFFSET … #define EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT … #define EXYNOS3250_CHROMA_CR_YY_OFFSET_MASK … #define EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT … #define EXYNOS3250_CHROMA_CR_YX_OFFSET_MASK … /* Raw image data r/w address register */ #define EXYNOS3250_JPG_IMGADR … /* Source or destination JPEG file DMA buffer address */ #define EXYNOS3250_JPG_JPGADR … /* Coefficients for RGB-to-YCbCr converter register */ #define EXYNOS3250_JPG_COEF(n) … #define EXYNOS3250_COEF_SHIFT(j) … #define EXYNOS3250_COEF_MASK(j) … /* Raw input format setting */ #define EXYNOS3250_JPGCMOD … #define EXYNOS3250_SRC_TILE_EN … #define EXYNOS3250_SRC_NV_MASK … #define EXYNOS3250_SRC_NV12 … #define EXYNOS3250_SRC_NV21 … #define EXYNOS3250_SRC_BIG_ENDIAN_MASK … #define EXYNOS3250_SRC_BIG_ENDIAN … #define EXYNOS3250_MODE_SEL_MASK … #define EXYNOS3250_MODE_SEL_420_2P … #define EXYNOS3250_MODE_SEL_422_1P_LUM_CHR … #define EXYNOS3250_MODE_SEL_RGB565 … #define EXYNOS3250_MODE_SEL_422_1P_CHR_LUM … #define EXYNOS3250_MODE_SEL_ARGB8888 … #define EXYNOS3250_MODE_SEL_420_3P … #define EXYNOS3250_SRC_SWAP_RGB … #define EXYNOS3250_SRC_SWAP_UV … #define EXYNOS3250_MODE_Y16_MASK … #define EXYNOS3250_MODE_Y16 … #define EXYNOS3250_HALF_EN_MASK … #define EXYNOS3250_HALF_EN … /* Power on/off and clock down control */ #define EXYNOS3250_JPGCLKCON … #define EXYNOS3250_CLK_DOWN_READY … #define EXYNOS3250_POWER_ON … /* Start compression or decompression */ #define EXYNOS3250_JSTART … /* Restart decompression after header analysis */ #define EXYNOS3250_JRSTART … /* JPEG SW reset register */ #define EXYNOS3250_SW_RESET … /* JPEG timer setting register */ #define EXYNOS3250_TIMER_SE … #define EXYNOS3250_TIMER_INT_EN_SHIFT … #define EXYNOS3250_TIMER_INT_EN … #define EXYNOS3250_TIMER_INIT_MASK … /* JPEG timer status register */ #define EXYNOS3250_TIMER_ST … #define EXYNOS3250_TIMER_INT_STAT_SHIFT … #define EXYNOS3250_TIMER_INT_STAT … #define EXYNOS3250_TIMER_CNT_SHIFT … #define EXYNOS3250_TIMER_CNT_MASK … /* Command status register */ #define EXYNOS3250_COMSTAT … #define EXYNOS3250_CUR_PROC_MODE … #define EXYNOS3250_CUR_COM_MODE … /* JPEG decompression output format register */ #define EXYNOS3250_OUTFORM … #define EXYNOS3250_OUT_ALPHA_MASK … #define EXYNOS3250_OUT_TILE_EN … #define EXYNOS3250_OUT_NV_MASK … #define EXYNOS3250_OUT_NV12 … #define EXYNOS3250_OUT_NV21 … #define EXYNOS3250_OUT_BIG_ENDIAN_MASK … #define EXYNOS3250_OUT_BIG_ENDIAN … #define EXYNOS3250_OUT_SWAP_RGB … #define EXYNOS3250_OUT_SWAP_UV … #define EXYNOS3250_OUT_FMT_MASK … #define EXYNOS3250_OUT_FMT_420_2P … #define EXYNOS3250_OUT_FMT_422_1P_LUM_CHR … #define EXYNOS3250_OUT_FMT_422_1P_CHR_LUM … #define EXYNOS3250_OUT_FMT_420_3P … #define EXYNOS3250_OUT_FMT_RGB565 … #define EXYNOS3250_OUT_FMT_ARGB8888 … /* Input JPEG stream byte size for decompression */ #define EXYNOS3250_DEC_STREAM_SIZE … #define EXYNOS3250_DEC_STREAM_MASK … /* The upper bound of the byte size of output compressed stream */ #define EXYNOS3250_ENC_STREAM_BOUND … #define EXYNOS3250_ENC_STREAM_BOUND_MASK … /* Scale-down ratio when decoding */ #define EXYNOS3250_DEC_SCALING_RATIO … #define EXYNOS3250_DEC_SCALE_FACTOR_MASK … #define EXYNOS3250_DEC_SCALE_FACTOR_8_8 … #define EXYNOS3250_DEC_SCALE_FACTOR_4_8 … #define EXYNOS3250_DEC_SCALE_FACTOR_2_8 … #define EXYNOS3250_DEC_SCALE_FACTOR_1_8 … /* Error check */ #define EXYNOS3250_CRC_RESULT … /* RDMA and WDMA operation status register */ #define EXYNOS3250_DMA_OPER_STATUS … #define EXYNOS3250_WDMA_OPER_STATUS … #define EXYNOS3250_RDMA_OPER_STATUS … /* DMA issue gathering number and issue number settings */ #define EXYNOS3250_DMA_ISSUE_NUM … #define EXYNOS3250_WDMA_ISSUE_NUM_SHIFT … #define EXYNOS3250_WDMA_ISSUE_NUM_MASK … #define EXYNOS3250_RDMA_ISSUE_NUM_SHIFT … #define EXYNOS3250_RDMA_ISSUE_NUM_MASK … #define EXYNOS3250_ISSUE_GATHER_NUM_SHIFT … #define EXYNOS3250_ISSUE_GATHER_NUM_MASK … #define EXYNOS3250_DMA_MO_COUNT … /* Version register */ #define EXYNOS3250_VERSION … /* RGB <-> YUV conversion coefficients */ #define EXYNOS3250_JPEG_ENC_COEF1 … #define EXYNOS3250_JPEG_ENC_COEF2 … #define EXYNOS3250_JPEG_ENC_COEF3 … #define EXYNOS3250_JPEG_DEC_COEF1 … #define EXYNOS3250_JPEG_DEC_COEF2 … #define EXYNOS3250_JPEG_DEC_COEF3 … #endif /* JPEG_REGS_H_ */
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