/* SPDX-License-Identifier: GPL-2.0-only */ /* * Register definition file for Samsung MFC V5.1 Interface (FIMV) driver * * Kamil Debski, Copyright (c) 2010 Samsung Electronics * http://www.samsung.com/ */ #ifndef _REGS_FIMV_H #define _REGS_FIMV_H #include <linux/kernel.h> #include <linux/sizes.h> #define S5P_FIMV_REG_SIZE … #define S5P_FIMV_REG_COUNT … /* Number of bits that the buffer address should be shifted for particular * MFC buffers. */ #define S5P_FIMV_START_ADDR … #define S5P_FIMV_END_ADDR … #define S5P_FIMV_SW_RESET … #define S5P_FIMV_RISC_HOST_INT … /* Command from HOST to RISC */ #define S5P_FIMV_HOST2RISC_CMD … #define S5P_FIMV_HOST2RISC_ARG1 … #define S5P_FIMV_HOST2RISC_ARG2 … #define S5P_FIMV_HOST2RISC_ARG3 … #define S5P_FIMV_HOST2RISC_ARG4 … /* Command from RISC to HOST */ #define S5P_FIMV_RISC2HOST_CMD … #define S5P_FIMV_RISC2HOST_CMD_MASK … #define S5P_FIMV_RISC2HOST_ARG1 … #define S5P_FIMV_RISC2HOST_ARG2 … #define S5P_FIMV_RISC2HOST_ARG3 … #define S5P_FIMV_RISC2HOST_ARG4 … #define S5P_FIMV_FW_VERSION … #define S5P_FIMV_SYS_MEM_SZ … #define S5P_FIMV_FW_STATUS … /* Memory controller register */ #define S5P_FIMV_MC_DRAMBASE_ADR_A … #define S5P_FIMV_MC_DRAMBASE_ADR_B … #define S5P_FIMV_MC_STATUS … /* Common register */ #define S5P_FIMV_COMMON_BASE_A … #define S5P_FIMV_COMMON_BASE_B … /* Decoder */ #define S5P_FIMV_DEC_CHROMA_ADR … #define S5P_FIMV_DEC_LUMA_ADR … /* H.264 decoding */ #define S5P_FIMV_H264_VERT_NB_MV_ADR … /* vertical neighbor motion vector */ #define S5P_FIMV_H264_NB_IP_ADR … /* neighbor pixels for intra pred */ #define S5P_FIMV_H264_MV_ADR … /* H264 motion vector */ /* MPEG4 decoding */ #define S5P_FIMV_MPEG4_NB_DCAC_ADR … /* neighbor AC/DC coeff. */ #define S5P_FIMV_MPEG4_UP_NB_MV_ADR … /* upper neighbor motion vector */ #define S5P_FIMV_MPEG4_SA_MV_ADR … /* subseq. anchor motion vector */ #define S5P_FIMV_MPEG4_OT_LINE_ADR … /* overlap transform line */ #define S5P_FIMV_MPEG4_SP_ADR … /* syntax parser */ /* H.263 decoding */ #define S5P_FIMV_H263_NB_DCAC_ADR … #define S5P_FIMV_H263_UP_NB_MV_ADR … #define S5P_FIMV_H263_SA_MV_ADR … #define S5P_FIMV_H263_OT_LINE_ADR … /* VC-1 decoding */ #define S5P_FIMV_VC1_NB_DCAC_ADR … #define S5P_FIMV_VC1_UP_NB_MV_ADR … #define S5P_FIMV_VC1_SA_MV_ADR … #define S5P_FIMV_VC1_OT_LINE_ADR … #define S5P_FIMV_VC1_BITPLANE3_ADR … /* bitplane3 */ #define S5P_FIMV_VC1_BITPLANE2_ADR … /* bitplane2 */ #define S5P_FIMV_VC1_BITPLANE1_ADR … /* bitplane1 */ /* Encoder */ #define S5P_FIMV_ENC_REF0_LUMA_ADR … #define S5P_FIMV_ENC_REF1_LUMA_ADR … /* reconstructed luma */ #define S5P_FIMV_ENC_REF0_CHROMA_ADR … #define S5P_FIMV_ENC_REF1_CHROMA_ADR … /* reconstructed chroma */ #define S5P_FIMV_ENC_REF2_LUMA_ADR … #define S5P_FIMV_ENC_REF2_CHROMA_ADR … #define S5P_FIMV_ENC_REF3_LUMA_ADR … #define S5P_FIMV_ENC_REF3_CHROMA_ADR … /* H.264 encoding */ #define S5P_FIMV_H264_UP_MV_ADR … /* upper motion vector */ #define S5P_FIMV_H264_NBOR_INFO_ADR … /* entropy engine's neighbor info. */ #define S5P_FIMV_H264_UP_INTRA_MD_ADR … /* upper intra MD */ #define S5P_FIMV_H264_COZERO_FLAG_ADR … /* direct cozero flag */ #define S5P_FIMV_H264_UP_INTRA_PRED_ADR … /* upper intra PRED */ /* H.263 encoding */ #define S5P_FIMV_H263_UP_MV_ADR … /* upper motion vector */ #define S5P_FIMV_H263_ACDC_COEF_ADR … /* upper Q coeff. */ /* MPEG4 encoding */ #define S5P_FIMV_MPEG4_UP_MV_ADR … /* upper motion vector */ #define S5P_FIMV_MPEG4_ACDC_COEF_ADR … /* upper Q coeff. */ #define S5P_FIMV_MPEG4_COZERO_FLAG_ADR … /* direct cozero flag */ #define S5P_FIMV_ENC_REF_B_LUMA_ADR … #define S5P_FIMV_ENC_REF_B_CHROMA_ADR … #define S5P_FIMV_ENC_CUR_LUMA_ADR … #define S5P_FIMV_ENC_CUR_CHROMA_ADR … /* Codec common register */ #define S5P_FIMV_ENC_HSIZE_PX … #define S5P_FIMV_ENC_VSIZE_PX … #define S5P_FIMV_ENC_PROFILE … #define S5P_FIMV_ENC_PROFILE_H264_MAIN … #define S5P_FIMV_ENC_PROFILE_H264_HIGH … #define S5P_FIMV_ENC_PROFILE_H264_BASELINE … #define S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE … #define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE … #define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE … #define S5P_FIMV_ENC_PIC_STRUCT … #define S5P_FIMV_ENC_LF_CTRL … #define S5P_FIMV_ENC_ALPHA_OFF … #define S5P_FIMV_ENC_BETA_OFF … #define S5P_FIMV_MR_BUSIF_CTRL … #define S5P_FIMV_ENC_PXL_CACHE_CTRL … /* Channel & stream interface register */ #define S5P_FIMV_SI_RTN_CHID … #define S5P_FIMV_SI_CH0_INST_ID … #define S5P_FIMV_SI_CH1_INST_ID … /* Decoder */ #define S5P_FIMV_SI_VRESOL … #define S5P_FIMV_SI_HRESOL … #define S5P_FIMV_SI_BUF_NUMBER … #define S5P_FIMV_SI_DISPLAY_Y_ADR … #define S5P_FIMV_SI_DISPLAY_C_ADR … #define S5P_FIMV_SI_CONSUMED_BYTES … #define S5P_FIMV_SI_DISPLAY_STATUS … #define S5P_FIMV_SI_DECODE_Y_ADR … #define S5P_FIMV_SI_DECODE_C_ADR … #define S5P_FIMV_SI_DECODE_STATUS … #define S5P_FIMV_SI_CH0_SB_ST_ADR … #define S5P_FIMV_SI_CH0_SB_FRM_SIZE … #define S5P_FIMV_SI_CH0_DESC_ADR … #define S5P_FIMV_SI_CH0_CPB_SIZE … #define S5P_FIMV_SI_CH0_DESC_SIZE … #define S5P_FIMV_SI_CH1_SB_ST_ADR … #define S5P_FIMV_SI_CH1_SB_FRM_SIZE … #define S5P_FIMV_SI_CH1_DESC_ADR … #define S5P_FIMV_SI_CH1_CPB_SIZE … #define S5P_FIMV_SI_CH1_DESC_SIZE … #define S5P_FIMV_CRC_LUMA0 … #define S5P_FIMV_CRC_CHROMA0 … #define S5P_FIMV_CRC_LUMA1 … #define S5P_FIMV_CRC_CHROMA1 … /* Display status */ #define S5P_FIMV_DEC_STATUS_DECODING_ONLY … #define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY … #define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY … #define S5P_FIMV_DEC_STATUS_DECODING_EMPTY … #define S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK … #define S5P_FIMV_DEC_STATUS_PROGRESSIVE … #define S5P_FIMV_DEC_STATUS_INTERLACE … #define S5P_FIMV_DEC_STATUS_INTERLACE_MASK … #define S5P_FIMV_DEC_STATUS_CRC_NUMBER_TWO … #define S5P_FIMV_DEC_STATUS_CRC_NUMBER_FOUR … #define S5P_FIMV_DEC_STATUS_CRC_NUMBER_MASK … #define S5P_FIMV_DEC_STATUS_CRC_GENERATED … #define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED … #define S5P_FIMV_DEC_STATUS_CRC_MASK … #define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK … #define S5P_FIMV_DEC_STATUS_RESOLUTION_INC … #define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC … #define S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT … /* Decode frame address */ #define S5P_FIMV_DECODE_Y_ADR … #define S5P_FIMV_DECODE_C_ADR … /* Decoded frame tpe */ #define S5P_FIMV_DECODE_FRAME_TYPE … #define S5P_FIMV_DECODE_FRAME_MASK … #define S5P_FIMV_DECODE_FRAME_SKIPPED … #define S5P_FIMV_DECODE_FRAME_I_FRAME … #define S5P_FIMV_DECODE_FRAME_P_FRAME … #define S5P_FIMV_DECODE_FRAME_B_FRAME … #define S5P_FIMV_DECODE_FRAME_OTHER_FRAME … /* Sizes of buffers required for decoding */ #define S5P_FIMV_DEC_NB_IP_SIZE … #define S5P_FIMV_DEC_VERT_NB_MV_SIZE … #define S5P_FIMV_DEC_NB_DCAC_SIZE … #define S5P_FIMV_DEC_UPNB_MV_SIZE … #define S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE … #define S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE … #define S5P_FIMV_DEC_VC1_BITPLANE_SIZE … #define S5P_FIMV_DEC_STX_PARSER_SIZE … #define S5P_FIMV_DEC_BUF_ALIGN … #define S5P_FIMV_ENC_BUF_ALIGN … #define S5P_FIMV_NV12M_HALIGN … #define S5P_FIMV_NV12M_LVALIGN … #define S5P_FIMV_NV12M_CVALIGN … #define S5P_FIMV_NV12MT_HALIGN … #define S5P_FIMV_NV12MT_VALIGN … #define S5P_FIMV_NV12M_SALIGN … #define S5P_FIMV_NV12MT_SALIGN … /* Sizes of buffers required for encoding */ #define S5P_FIMV_ENC_UPMV_SIZE … #define S5P_FIMV_ENC_COLFLG_SIZE … #define S5P_FIMV_ENC_INTRAMD_SIZE … #define S5P_FIMV_ENC_INTRAPRED_SIZE … #define S5P_FIMV_ENC_NBORINFO_SIZE … #define S5P_FIMV_ENC_ACDCCOEF_SIZE … /* Encoder */ #define S5P_FIMV_ENC_SI_STRM_SIZE … #define S5P_FIMV_ENC_SI_PIC_CNT … #define S5P_FIMV_ENC_SI_WRITE_PTR … #define S5P_FIMV_ENC_SI_SLICE_TYPE … #define S5P_FIMV_ENC_SI_SLICE_TYPE_NON_CODED … #define S5P_FIMV_ENC_SI_SLICE_TYPE_I … #define S5P_FIMV_ENC_SI_SLICE_TYPE_P … #define S5P_FIMV_ENC_SI_SLICE_TYPE_B … #define S5P_FIMV_ENC_SI_SLICE_TYPE_SKIPPED … #define S5P_FIMV_ENC_SI_SLICE_TYPE_OTHERS … #define S5P_FIMV_ENCODED_Y_ADDR … #define S5P_FIMV_ENCODED_C_ADDR … #define S5P_FIMV_ENC_SI_CH0_SB_ADR … #define S5P_FIMV_ENC_SI_CH0_SB_SIZE … #define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR … #define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR … #define S5P_FIMV_ENC_SI_CH0_FRAME_INS … #define S5P_FIMV_ENC_SI_CH1_SB_ADR … #define S5P_FIMV_ENC_SI_CH1_SB_SIZE … #define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR … #define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR … #define S5P_FIMV_ENC_SI_CH1_FRAME_INS … #define S5P_FIMV_ENC_PIC_TYPE_CTRL … #define S5P_FIMV_ENC_B_RECON_WRITE_ON … #define S5P_FIMV_ENC_MSLICE_CTRL … #define S5P_FIMV_ENC_MSLICE_MB … #define S5P_FIMV_ENC_MSLICE_BIT … #define S5P_FIMV_ENC_CIR_CTRL … #define S5P_FIMV_ENC_MAP_FOR_CUR … #define S5P_FIMV_ENC_PADDING_CTRL … #define S5P_FIMV_ENC_RC_CONFIG … #define S5P_FIMV_ENC_RC_BIT_RATE … #define S5P_FIMV_ENC_RC_QBOUND … #define S5P_FIMV_ENC_RC_RPARA … #define S5P_FIMV_ENC_RC_MB_CTRL … /* Encoder for H264 only */ #define S5P_FIMV_ENC_H264_ENTROPY_MODE … #define S5P_FIMV_ENC_H264_ALPHA_OFF … #define S5P_FIMV_ENC_H264_BETA_OFF … #define S5P_FIMV_ENC_H264_NUM_OF_REF … #define S5P_FIMV_ENC_H264_TRANS_FLAG … #define S5P_FIMV_ENC_RC_FRAME_RATE … /* Encoder for MPEG4 only */ #define S5P_FIMV_ENC_MPEG4_QUART_PXL … /* Additional */ #define S5P_FIMV_SI_CH0_DPB_CONF_CTRL … #define S5P_FIMV_SLICE_INT_MASK … #define S5P_FIMV_SLICE_INT_SHIFT … #define S5P_FIMV_DDELAY_ENA_SHIFT … #define S5P_FIMV_DDELAY_VAL_MASK … #define S5P_FIMV_DDELAY_VAL_SHIFT … #define S5P_FIMV_DPB_COUNT_MASK … #define S5P_FIMV_DPB_FLUSH_MASK … #define S5P_FIMV_DPB_FLUSH_SHIFT … #define S5P_FIMV_SI_CH0_RELEASE_BUF … #define S5P_FIMV_SI_CH0_HOST_WR_ADR … /* Codec numbers */ #define S5P_FIMV_CODEC_NONE … #define S5P_FIMV_CODEC_H264_DEC … #define S5P_FIMV_CODEC_VC1_DEC … #define S5P_FIMV_CODEC_MPEG4_DEC … #define S5P_FIMV_CODEC_MPEG2_DEC … #define S5P_FIMV_CODEC_H263_DEC … #define S5P_FIMV_CODEC_VC1RCV_DEC … #define S5P_FIMV_CODEC_H264_ENC … #define S5P_FIMV_CODEC_MPEG4_ENC … #define S5P_FIMV_CODEC_H263_ENC … /* Channel Control Register */ #define S5P_FIMV_CH_SEQ_HEADER … #define S5P_FIMV_CH_FRAME_START … #define S5P_FIMV_CH_LAST_FRAME … #define S5P_FIMV_CH_INIT_BUFS … #define S5P_FIMV_CH_FRAME_START_REALLOC … #define S5P_FIMV_CH_MASK … #define S5P_FIMV_CH_SHIFT … /* Host to RISC command */ #define S5P_FIMV_H2R_CMD_EMPTY … #define S5P_FIMV_H2R_CMD_OPEN_INSTANCE … #define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE … #define S5P_FIMV_H2R_CMD_SYS_INIT … #define S5P_FIMV_H2R_CMD_FLUSH … #define S5P_FIMV_H2R_CMD_SLEEP … #define S5P_FIMV_H2R_CMD_WAKEUP … #define S5P_FIMV_R2H_CMD_EMPTY … #define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET … #define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET … #define S5P_FIMV_R2H_CMD_RSV_RET … #define S5P_FIMV_R2H_CMD_SEQ_DONE_RET … #define S5P_FIMV_R2H_CMD_FRAME_DONE_RET … #define S5P_FIMV_R2H_CMD_SLICE_DONE_RET … #define S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET … #define S5P_FIMV_R2H_CMD_SYS_INIT_RET … #define S5P_FIMV_R2H_CMD_FW_STATUS_RET … #define S5P_FIMV_R2H_CMD_SLEEP_RET … #define S5P_FIMV_R2H_CMD_WAKEUP_RET … #define S5P_FIMV_R2H_CMD_FLUSH_RET … #define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET … #define S5P_FIMV_R2H_CMD_EDFU_INIT_RET … #define S5P_FIMV_R2H_CMD_ERR_RET … /* Dummy definition for MFCv6 compatibility */ #define S5P_FIMV_CODEC_H264_MVC_DEC … #define S5P_FIMV_R2H_CMD_FIELD_DONE_RET … #define S5P_FIMV_MFC_RESET … #define S5P_FIMV_RISC_ON … #define S5P_FIMV_RISC_BASE_ADDRESS … #define S5P_FIMV_CODEC_VP8_DEC … #define S5P_FIMV_REG_CLEAR_BEGIN … #define S5P_FIMV_REG_CLEAR_COUNT … /* Error handling defines */ #define S5P_FIMV_ERR_NO_VALID_SEQ_HDR … #define S5P_FIMV_ERR_INCOMPLETE_FRAME … #define S5P_FIMV_ERR_TIMEOUT … #define S5P_FIMV_ERR_WARNINGS_START … #define S5P_FIMV_ERR_DEC_MASK … #define S5P_FIMV_ERR_DEC_SHIFT … #define S5P_FIMV_ERR_DSPL_MASK … #define S5P_FIMV_ERR_DSPL_SHIFT … /* Shared memory registers' offsets */ /* An offset of the start position in the stream when * the start position is not aligned */ #define S5P_FIMV_SHARED_CROP_INFO_H … #define S5P_FIMV_SHARED_CROP_LEFT_MASK … #define S5P_FIMV_SHARED_CROP_LEFT_SHIFT … #define S5P_FIMV_SHARED_CROP_RIGHT_MASK … #define S5P_FIMV_SHARED_CROP_RIGHT_SHIFT … #define S5P_FIMV_SHARED_CROP_INFO_V … #define S5P_FIMV_SHARED_CROP_TOP_MASK … #define S5P_FIMV_SHARED_CROP_TOP_SHIFT … #define S5P_FIMV_SHARED_CROP_BOTTOM_MASK … #define S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT … #define S5P_FIMV_SHARED_SET_FRAME_TAG … #define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP … #define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT … #define S5P_FIMV_SHARED_START_BYTE_NUM … #define S5P_FIMV_SHARED_RC_VOP_TIMING … #define S5P_FIMV_SHARED_LUMA_DPB_SIZE … #define S5P_FIMV_SHARED_CHROMA_DPB_SIZE … #define S5P_FIMV_SHARED_MV_SIZE … #define S5P_FIMV_SHARED_PIC_TIME_TOP … #define S5P_FIMV_SHARED_PIC_TIME_BOTTOM … #define S5P_FIMV_SHARED_EXT_ENC_CONTROL … #define S5P_FIMV_SHARED_P_B_FRAME_QP … #define S5P_FIMV_SHARED_ASPECT_RATIO_IDC … #define S5P_FIMV_SHARED_EXTENDED_SAR … #define S5P_FIMV_SHARED_H264_I_PERIOD … #define S5P_FIMV_SHARED_RC_CONTROL_CONFIG … #define S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT … /* Offset used by the hardware to store addresses */ #define MFC_OFFSET_SHIFT … #define FIRMWARE_ALIGN … #define MFC_H264_CTX_BUF_SIZE … #define MFC_CTX_BUF_SIZE … #define DESC_BUF_SIZE … #define SHARED_BUF_SIZE … #define DEF_CPB_SIZE … #define MAX_CPB_SIZE … #define MAX_FW_SIZE … #define MFC_VERSION … #define MFC_NUM_PORTS … #define S5P_FIMV_SHARED_FRAME_PACK_SEI_AVAIL … #define S5P_FIMV_SHARED_FRAME_PACK_ARRGMENT_ID … #define S5P_FIMV_SHARED_FRAME_PACK_SEI_INFO … #define S5P_FIMV_SHARED_FRAME_PACK_GRID_POS … /* Values for resolution change in display status */ #define S5P_FIMV_RES_INCREASE … #define S5P_FIMV_RES_DECREASE … #endif /* _REGS_FIMV_H */
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