/* SPDX-License-Identifier: GPL-2.0-only */ /* * Register definition file for Samsung MFC V8.x Interface (FIMV) driver * * Copyright (c) 2014 Samsung Electronics Co., Ltd. * http://www.samsung.com/ */ #ifndef _REGS_MFC_V8_H #define _REGS_MFC_V8_H #include <linux/sizes.h> #include "regs-mfc-v7.h" /* Additional registers for v8 */ #define S5P_FIMV_D_MVC_NUM_VIEWS_V8 … #define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 … #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 … #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 … #define S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8 … #define S5P_FIMV_D_MV_BUFFER_SIZE_V8 … #define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 … #define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 … #define S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8 … #define S5P_FIMV_D_FIRST_PLANE_DPB_V8 … #define S5P_FIMV_D_SECOND_PLANE_DPB_V8 … #define S5P_FIMV_D_THIRD_PLANE_DPB_V8 … #define S5P_FIMV_D_MV_BUFFER_V8 … #define S5P_FIMV_D_NUM_MV_V8 … #define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8 … #define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8 … #define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8 … #define S5P_FIMV_D_CPB_BUFFER_ADDR_V8 … #define S5P_FIMV_D_CPB_BUFFER_SIZE_V8 … #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8 … #define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8 … #define S5P_FIMV_D_SLICE_IF_ENABLE_V8 … #define S5P_FIMV_D_STREAM_DATA_SIZE_V8 … /* Display information register */ #define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8 … #define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8 … /* Display status */ #define S5P_FIMV_D_DISPLAY_STATUS_V8 … #define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8 … #define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 … #define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8 … #define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8 … #define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8 … #define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8 … /* Decoded picture information register */ #define S5P_FIMV_D_DECODED_STATUS_V8 … #define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8 … #define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 … #define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8 … #define S5P_FIMV_D_DECODED_FRAME_TYPE_V8 … #define S5P_FIMV_D_DECODED_NAL_SIZE_V8 … /* Returned value register for specific setting */ #define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8 … #define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8 … #define S5P_FIMV_D_MVC_VIEW_ID_V8 … /* SEI related information */ #define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8 … /* Encoder Registers */ #define S5P_FIMV_E_FIXED_PICTURE_QP_V8 … #define S5P_FIMV_E_RC_CONFIG_V8 … #define S5P_FIMV_E_RC_QP_BOUND_V8 … #define S5P_FIMV_E_RC_RPARAM_V8 … #define S5P_FIMV_E_MB_RC_CONFIG_V8 … #define S5P_FIMV_E_PADDING_CTRL_V8 … #define S5P_FIMV_E_MV_HOR_RANGE_V8 … #define S5P_FIMV_E_MV_VER_RANGE_V8 … #define S5P_FIMV_E_VBV_BUFFER_SIZE_V8 … #define S5P_FIMV_E_VBV_INIT_DELAY_V8 … #define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8 … #define S5P_FIMV_E_ASPECT_RATIO_V8 … #define S5P_FIMV_E_EXTENDED_SAR_V8 … #define S5P_FIMV_E_H264_OPTIONS_V8 … /* MFCv8 Context buffer sizes */ #define MFC_CTX_BUF_SIZE_V8 … #define MFC_H264_DEC_CTX_BUF_SIZE_V8 … #define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 … #define MFC_H264_ENC_CTX_BUF_SIZE_V8 … #define MFC_OTHER_ENC_CTX_BUF_SIZE_V8 … /* Buffer size defines */ #define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h) … #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) … #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) … #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) … #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) … #define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) … /* BUffer alignment defines */ #define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8 … /* MFCv8 variant defines */ #define MAX_FW_SIZE_V8 … #define MAX_CPB_SIZE_V8 … #define MFC_VERSION_V8 … #define MFC_NUM_PORTS_V8 … #endif /*_REGS_MFC_V8_H*/
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