/* SPDX-License-Identifier: GPL-2.0 */ /* * c8sectpfe-core.h - C8SECTPFE STi DVB driver * * Copyright (c) STMicroelectronics 2015 * * Author:Peter Bennett <[email protected]> * Peter Griffin <[email protected]> * */ #ifndef _C8SECTPFE_CORE_H_ #define _C8SECTPFE_CORE_H_ #define C8SECTPFEI_MAXCHANNEL … #define C8SECTPFEI_MAXADAPTER … #define C8SECTPFE_MAX_TSIN_CHAN … struct gpio_desc; struct channel_info { … }; struct c8sectpfe_hw { … }; struct c8sectpfei { … }; /* C8SECTPFE SYS Regs list */ #define SYS_INPUT_ERR_STATUS … #define SYS_OTHER_ERR_STATUS … #define SYS_INPUT_ERR_MASK … #define SYS_OTHER_ERR_MASK … #define SYS_DMA_ROUTE … #define SYS_INPUT_CLKEN … #define IBENABLE_MASK … #define SYS_OTHER_CLKEN … #define TSDMAENABLE … #define MEMDMAENABLE … #define SYS_CFG_NUM_IB … #define SYS_CFG_NUM_MIB … #define SYS_CFG_NUM_SWTS … #define SYS_CFG_NUM_TSOUT … #define SYS_CFG_NUM_CCSC … #define SYS_CFG_NUM_RAM … #define SYS_CFG_NUM_TP … /* Input Block Regs */ #define C8SECTPFE_INPUTBLK_OFFSET … #define C8SECTPFE_CHANNEL_OFFSET(x) … #define C8SECTPFE_IB_IP_FMT_CFG(x) … #define C8SECTPFE_IGNORE_ERR_AT_SOP … #define C8SECTPFE_IGNORE_ERR_IN_PKT … #define C8SECTPFE_IGNORE_ERR_IN_BYTE … #define C8SECTPFE_INVERT_TSCLK … #define C8SECTPFE_ALIGN_BYTE_SOP … #define C8SECTPFE_ASYNC_NOT_SYNC … #define C8SECTPFE_BYTE_ENDIANNESS_MSB … #define C8SECTPFE_SERIAL_NOT_PARALLEL … #define C8SECTPFE_IB_SYNCLCKDRP_CFG(x) … #define C8SECTPFE_SYNC(x) … #define C8SECTPFE_DROP(x) … #define C8SECTPFE_TOKEN(x) … #define C8SECTPFE_SLDENDIANNESS … #define C8SECTPFE_IB_TAGBYTES_CFG(x) … #define C8SECTPFE_TAG_HEADER(x) … #define C8SECTPFE_TAG_COUNTER(x) … #define C8SECTPFE_TAG_ENABLE … #define C8SECTPFE_IB_PID_SET(x) … #define C8SECTPFE_PID_OFFSET(x) … #define C8SECTPFE_PID_NUMBITS(x) … #define C8SECTPFE_PID_ENABLE … #define C8SECTPFE_IB_PKT_LEN(x) … #define C8SECTPFE_IB_BUFF_STRT(x) … #define C8SECTPFE_IB_BUFF_END(x) … #define C8SECTPFE_IB_READ_PNT(x) … #define C8SECTPFE_IB_WRT_PNT(x) … #define C8SECTPFE_IB_PRI_THRLD(x) … #define C8SECTPFE_PRI_VALUE(x) … #define C8SECTPFE_PRI_LOWPRI(x) … #define C8SECTPFE_PRI_HIGHPRI(x) … #define C8SECTPFE_IB_STAT(x) … #define C8SECTPFE_STAT_FIFO_OVERFLOW(x) … #define C8SECTPFE_STAT_BUFFER_OVERFLOW(x) … #define C8SECTPFE_STAT_OUTOFORDERRP(x) … #define C8SECTPFE_STAT_PID_OVERFLOW(x) … #define C8SECTPFE_STAT_PKT_OVERFLOW(x) … #define C8SECTPFE_STAT_ERROR_PACKETS(x) … #define C8SECTPFE_STAT_SHORT_PACKETS(x) … #define C8SECTPFE_IB_MASK(x) … #define C8SECTPFE_MASK_FIFO_OVERFLOW … #define C8SECTPFE_MASK_BUFFER_OVERFLOW … #define C8SECTPFE_MASK_OUTOFORDERRP(x) … #define C8SECTPFE_MASK_PID_OVERFLOW(x) … #define C8SECTPFE_MASK_PKT_OVERFLOW(x) … #define C8SECTPFE_MASK_ERROR_PACKETS(x) … #define C8SECTPFE_MASK_SHORT_PACKETS(x) … #define C8SECTPFE_IB_SYS(x) … #define C8SECTPFE_SYS_RESET … #define C8SECTPFE_SYS_ENABLE … /* * Pointer record data structure required for each input block * see Table 82 on page 167 of functional specification. */ #define DMA_PRDS_MEMBASE … #define DMA_PRDS_MEMTOP … /* * TS packet size, including tag bytes added by input block, * rounded up to the next multiple of 8 bytes. The packet size, * including any tagging bytes and rounded up to the nearest * multiple of 8 bytes must be less than 255 bytes. */ #define DMA_PRDS_PKTSIZE … #define DMA_PRDS_TPENABLE … #define TP0_OFFSET … #define DMA_PRDS_BUSBASE_TP(x) … #define DMA_PRDS_BUSTOP_TP(x) … #define DMA_PRDS_BUSWP_TP(x) … #define DMA_PRDS_BUSRP_TP(x) … #define DMA_PRDS_SIZE … #define DMA_MEMDMA_OFFSET … #define DMA_IMEM_OFFSET … #define DMA_DMEM_OFFSET … #define DMA_CPU … #define DMA_PER_OFFSET … #define DMA_MEMDMA_DMEM … #define DMA_MEMDMA_IMEM … /* XP70 Slim core regs */ #define DMA_CPU_ID … #define DMA_CPU_VCR … #define DMA_CPU_RUN … #define DMA_CPU_CLOCKGATE … #define DMA_CPU_PC … /* Enable Interrupt for a IB */ #define DMA_PER_TPn_DREQ_MASK … /* Ack interrupt by setting corresponding bit */ #define DMA_PER_TPn_DACK_SET … #define DMA_PER_TPn_DREQ … #define DMA_PER_TPn_DACK … #define DMA_PER_DREQ_MODE … #define DMA_PER_STBUS_SYNC … #define DMA_PER_STBUS_ACCESS … #define DMA_PER_STBUS_ADDRESS … #define DMA_PER_IDLE_INT … #define DMA_PER_PRIORITY … #define DMA_PER_MAX_OPCODE … #define DMA_PER_MAX_CHUNK … #define DMA_PER_PAGE_SIZE … #define DMA_PER_MBOX_STATUS … #define DMA_PER_MBOX_SET … #define DMA_PER_MBOX_CLEAR … #define DMA_PER_MBOX_MASK … #define DMA_PER_INJECT_PKT_SRC … #define DMA_PER_INJECT_PKT_DEST … #define DMA_PER_INJECT_PKT_ADDR … #define DMA_PER_INJECT_PKT … #define DMA_PER_PAT_PTR_INIT … #define DMA_PER_PAT_PTR … #define DMA_PER_SLEEP_MASK … #define DMA_PER_SLEEP_COUNTER … /* #define DMA_RF_CPUREGn DMA_RFBASEADDR n=0 to 15) slim regsa */ /* The following are from DMA_DMEM_BaseAddress */ #define DMA_FIRMWARE_VERSION … #define DMA_PTRREC_BASE … #define DMA_PTRREC_INPUT_OFFSET … #define DMA_ERRREC_BASE … #define DMA_ERROR_RECORD(n) … #define DMA_IDLE_REQ … #define IDLEREQ … #define DMA_FIRMWARE_CONFIG … /* Regs for PID Filter */ #define PIDF_OFFSET … #define PIDF_BASE(n) … #define PIDF_LEAK_ENABLE … #define PIDF_LEAK_STATUS … #define PIDF_LEAK_COUNT_RESET … #define PIDF_LEAK_COUNTER … #endif /* _C8SECTPFE_CORE_H_ */
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