linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2020 Kévin L'hôpital <[email protected]>
 * Copyright 2020-2022 Bootlin
 * Author: Paul Kocialkowski <[email protected]>
 */

#ifndef _SUN8I_A83T_MIPI_CSI2_REG_H_
#define _SUN8I_A83T_MIPI_CSI2_REG_H_

#define SUN8I_A83T_MIPI_CSI2_VERSION_REG
#define SUN8I_A83T_MIPI_CSI2_CTRL_REG
#define SUN8I_A83T_MIPI_CSI2_CTRL_INIT_VALUE
#define SUN8I_A83T_MIPI_CSI2_CTRL_RESET_N
#define SUN8I_A83T_MIPI_CSI2_RX_PKT_NUM_REG
#define SUN8I_A83T_MIPI_CSI2_RX_PKT_NUM_INIT_VALUE
#define SUN8I_A83T_MIPI_CSI2_RSVD0_REG

#define SUN8I_A83T_MIPI_CSI2_RSVD1_REG
#define SUN8I_A83T_MIPI_CSI2_RSVD1_HW_LOCK_VALUE
#define SUN8I_A83T_MIPI_CSI2_RSVD2_REG
#define SUN8I_A83T_MIPI_CSI2_RSVD2_HW_LOCK_VALUE
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_REG
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_ECC_ERR_DBL
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT3
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT2
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT1
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT0
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LS_LE_ERR_DT3
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LS_LE_ERR_DT2
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LS_LE_ERR_DT1
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_LS_LE_ERR_DT0
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_CRC_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_CRC_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_CRC_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_CRC_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_FRM_SEQ_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_FRM_SEQ_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_FRM_SEQ_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_FRM_SEQ_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_FS_FE_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_FS_FE_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_FS_FE_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_FS_FE_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_SOT_SYNC_ERR_3
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_SOT_SYNC_ERR_2
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_SOT_SYNC_ERR_1
#define SUN8I_A83T_MIPI_CSI2_INT_STA0_SOT_SYNC_ERR_0
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_REG
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_LINE_SEQ_ERR_DT7
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_LINE_SEQ_ERR_DT6
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_LINE_SEQ_ERR_DT5
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_LINE_SEQ_ERR_DT4
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_LS_LE_ERR_DT7
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_LS_LE_ERR_DT6
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_LS_LE_ERR_DT5
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_LS_LE_ERR_DT4
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_DT_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_DT_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_DT_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_DT_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_ECC_ERR1_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_ECC_ERR1_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_ECC_ERR1_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_ECC_ERR1_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_3
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_2
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_1
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_0
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_ESC_ENTRY_ERR_3
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_ESC_ENTRY_ERR_2
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_ESC_ENTRY_ERR_1
#define SUN8I_A83T_MIPI_CSI2_INT_STA1_ESC_ENTRY_ERR_0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_REG
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_ECC_ERR_DBL
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CKSM_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CKSM_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CKSM_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CKSM_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LINE_SEQ_ERR_DT3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LINE_SEQ_ERR_DT2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LINE_SEQ_ERR_DT1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LINE_SEQ_ERR_DT0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LS_LE_ERR_DT3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LS_LE_ERR_DT2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LS_LE_ERR_DT1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LS_LE_ERR_DT0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CRC_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CRC_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CRC_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CRC_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FRM_SEQ_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FRM_SEQ_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FRM_SEQ_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FRM_SEQ_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FS_FE_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FS_FE_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FS_FE_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FS_FE_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_SOT_SYNC_ERR_3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_SOT_SYNC_ERR_2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_SOT_SYNC_ERR_1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK0_SOT_SYNC_ERR_0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_REG
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_DT_ERR_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_DT_ERR_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_DT_ERR_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_DT_ERR_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_ECC_ERR1_VC3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_ECC_ERR1_VC2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_ECC_ERR1_VC1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_ECC_ERR1_VC0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_SOT_ERR_3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_SOT_ERR_2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_SOT_ERR_1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_SOT_ERR_0
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_ESC_ENTRY_ERR_3
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_ESC_ENTRY_ERR_2
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_ESC_ENTRY_ERR_1
#define SUN8I_A83T_MIPI_CSI2_INT_MSK1_ESC_ENTRY_ERR_0

#define SUN8I_A83T_MIPI_CSI2_CFG_REG
#define SUN8I_A83T_MIPI_CSI2_CFG_INIT_VALUE
#define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_EN
#define SUN8I_A83T_MIPI_CSI2_CFG_BYPASS_ECC_EN
#define SUN8I_A83T_MIPI_CSI2_CFG_UNPKT_EN
#define SUN8I_A83T_MIPI_CSI2_CFG_NONE_UNPKT_RX_MODE
#define SUN8I_A83T_MIPI_CSI2_CFG_YC_SWAB
#define SUN8I_A83T_MIPI_CSI2_CFG_N_BYTE
#define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_DLY_CYCLE(v)
#define SUN8I_A83T_MIPI_CSI2_CFG_N_CHANNEL(v)
#define SUN8I_A83T_MIPI_CSI2_CFG_N_LANE(v)
#define SUN8I_A83T_MIPI_CSI2_VCDT0_REG
#define SUN8I_A83T_MIPI_CSI2_VCDT0_CH_VC(ch, vc)
#define SUN8I_A83T_MIPI_CSI2_VCDT0_CH_DT(ch, t)
#define SUN8I_A83T_MIPI_CSI2_VCDT1_REG
#define SUN8I_A83T_MIPI_CSI2_VCDT1_CH_VC(ch, vc)
#define SUN8I_A83T_MIPI_CSI2_VCDT1_CH_DT(ch, t)

#endif