/* SPDX-License-Identifier: GPL-2.0-only */ /* * isp.h * * TI OMAP3 ISP - Core * * Copyright (C) 2009-2010 Nokia Corporation * Copyright (C) 2009 Texas Instruments, Inc. * * Contacts: Laurent Pinchart <[email protected]> * Sakari Ailus <[email protected]> */ #ifndef OMAP3_ISP_CORE_H #define OMAP3_ISP_CORE_H #include <media/media-entity.h> #include <media/v4l2-async.h> #include <media/v4l2-device.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/io.h> #include <linux/platform_device.h> #include <linux/wait.h> #include "omap3isp.h" #include "ispstat.h" #include "ispccdc.h" #include "ispreg.h" #include "ispresizer.h" #include "isppreview.h" #include "ispcsiphy.h" #include "ispcsi2.h" #include "ispccp2.h" #define ISP_TOK_TERM … #define to_isp_device(ptr_module) … #define to_device(ptr_module) … enum isp_mem_resources { … }; enum isp_sbl_resource { … }; enum isp_subclk_resource { … }; /* ISP: OMAP 34xx ES 1.0 */ #define ISP_REVISION_1_0 … /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */ #define ISP_REVISION_2_0 … /* ISP2P: OMAP 36xx */ #define ISP_REVISION_15_0 … #define ISP_PHY_TYPE_3430 … #define ISP_PHY_TYPE_3630 … struct regmap; /* * struct isp_res_mapping - Map ISP io resources to ISP revision. * @isp_rev: ISP_REVISION_x_x * @offset: register offsets of various ISP sub-blocks * @phy_type: ISP_PHY_TYPE_{3430,3630} */ struct isp_res_mapping { … }; /* * struct isp_reg - Structure for ISP register values. * @reg: 32-bit Register address. * @val: 32-bit Register value. */ struct isp_reg { … }; enum isp_xclk_id { … }; struct isp_xclk { … }; /* * struct isp_device - ISP device structure. * @dev: Device pointer specific to the OMAP3 ISP. * @revision: Stores current ISP module revision. * @irq_num: Currently used IRQ number. * @mmio_base: Array with kernel base addresses for ioremapped ISP register * regions. * @mmio_hist_base_phys: Physical L4 bus address for ISP hist block register * region. * @syscon: Regmap for the syscon register space * @syscon_offset: Offset of the CSIPHY control register in syscon * @phy_type: ISP_PHY_TYPE_{3430,3630} * @mapping: IOMMU mapping * @stat_lock: Spinlock for handling statistics * @isp_mutex: Mutex for serializing requests to ISP. * @stop_failure: Indicates that an entity failed to stop. * @crashed: Crashed ent_enum * @has_context: Context has been saved at least once and can be restored. * @ref_count: Reference count for handling multiple ISP requests. * @cam_ick: Pointer to camera interface clock structure. * @cam_mclk: Pointer to camera functional clock structure. * @csi2_fck: Pointer to camera CSI2 complexIO clock structure. * @l3_ick: Pointer to OMAP3 L3 bus interface clock. * @xclks: External clocks provided by the ISP * @irq: Currently attached ISP ISR callbacks information structure. * @isp_af: Pointer to current settings for ISP AutoFocus SCM. * @isp_hist: Pointer to current settings for ISP Histogram SCM. * @isp_h3a: Pointer to current settings for ISP Auto Exposure and * White Balance SCM. * @isp_res: Pointer to current settings for ISP Resizer. * @isp_prev: Pointer to current settings for ISP Preview. * @isp_ccdc: Pointer to current settings for ISP CCDC. * @platform_cb: ISP driver callback function pointers for platform code * * This structure is used to store the OMAP ISP Information. */ struct isp_device { … }; struct isp_async_subdev { … }; static inline struct isp_bus_cfg * v4l2_subdev_to_bus_cfg(struct v4l2_subdev *sd) { … } #define v4l2_dev_to_isp_device(dev) … void omap3isp_hist_dma_done(struct isp_device *isp); void omap3isp_flush(struct isp_device *isp); int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, atomic_t *stopping); int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait, atomic_t *stopping); int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe, enum isp_pipeline_stream_state state); void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe); void omap3isp_configure_bridge(struct isp_device *isp, enum ccdc_input_entity input, const struct isp_parallel_cfg *buscfg, unsigned int shift, unsigned int bridge); struct isp_device *omap3isp_get(struct isp_device *isp); void omap3isp_put(struct isp_device *isp); void omap3isp_print_status(struct isp_device *isp); void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res); void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res); void omap3isp_subclk_enable(struct isp_device *isp, enum isp_subclk_resource res); void omap3isp_subclk_disable(struct isp_device *isp, enum isp_subclk_resource res); int omap3isp_register_entities(struct platform_device *pdev, struct v4l2_device *v4l2_dev); void omap3isp_unregister_entities(struct platform_device *pdev); /* * isp_reg_readl - Read value of an OMAP3 ISP register * @isp: Device pointer specific to the OMAP3 ISP. * @isp_mmio_range: Range to which the register offset refers to. * @reg_offset: Register offset to read from. * * Returns an unsigned 32 bit value with the required register contents. */ static inline u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range, u32 reg_offset) { … } /* * isp_reg_writel - Write value to an OMAP3 ISP register * @isp: Device pointer specific to the OMAP3 ISP. * @reg_value: 32 bit value to write to the register. * @isp_mmio_range: Range to which the register offset refers to. * @reg_offset: Register offset to write into. */ static inline void isp_reg_writel(struct isp_device *isp, u32 reg_value, enum isp_mem_resources isp_mmio_range, u32 reg_offset) { … } /* * isp_reg_clr - Clear individual bits in an OMAP3 ISP register * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @clr_bits: 32 bit value which would be cleared in the register. */ static inline void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range, u32 reg, u32 clr_bits) { … } /* * isp_reg_set - Set individual bits in an OMAP3 ISP register * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @set_bits: 32 bit value which would be set in the register. */ static inline void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range, u32 reg, u32 set_bits) { … } /* * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @clr_bits: 32 bit value which would be cleared in the register. * @set_bits: 32 bit value which would be set in the register. * * The clear operation is done first, and then the set operation. */ static inline void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range, u32 reg, u32 clr_bits, u32 set_bits) { … } static inline enum v4l2_buf_type isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad) { … } #endif /* OMAP3_ISP_CORE_H */
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